Error control apparatus and method for channel equalizer
AssigneeLG Electronics Inc.
InventorGang-Ho Kim
Life of this patent
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Abstract
A channel equalizer includes an equalizer filter for correcting an error upon receipt of a signal transmitted by a sending end, a DD slicer for calculating a first error upon receipt of the corrected signal from the equalizer filter, a Sato slicer for calculating a second error upon receipt of the corrected signal from the equalizer filter, and a DD error size calculation unit for taking the absolute value of the real part and imaginary part of the first error calculated from the DD slicer and summing these absolute values.
Claims11
A channel equalizer comprising:
- an equalizer filter for correcting an error upon receipt of a signal transmitted by a sending end;
- a decision-directed (DD) slicer for calculating a first error upon receipt of the corrected signal from the equalizer filter;
- a Sato slicer for calculating a second error upon receipt of the corrected signal from the equalizer filter;
- a DD error size calculation unit for taking the absolute value of a real part and an imaginary part of the first error calculated from the DD slicer, and summing the absolute value of the real part and the absolute value of the imaginary part of the first error to obtain a sum;
- a first multiplier to multiple the second error output from the Sato slicer by a first scale constant;
- and
- a second multiplier to multiply a resultant output of the first multiplier by the sum output from the DD error size calculation unit.
An error control method for a channel equalizer, comprising the steps of:
- generating an error corrected signal by an equalizer filter;
- multiplying a first error calculated from a decision-directed (DD) slicer and a second error calculated from a Sato slicer using the error corrected signal, by first and second scale constants, respectively;
- taking the absolute value of a real part and an imaginary part of the first error calculated from the DD slicer, and summing the absolute value of the real part and the absolute value of the imaginary part of the first error to obtain a sum;
- obtaining the absolute value of an inverse response signal of a channel by multiplying the sum by the second error multiplied by the second scale constant and adding the resultant value to the first error multiplied by the first scale constant;
- and
- generating a filter tap coefficient to reproduce a signal transmitted from a sending end by feeding back the absolute value of the inverse response signal of the channel to the equalizer filter.
A channel equalizer comprising:
- first means for correcting an error upon receipt of a signal transmitted by a sending end;
- second means for calculating a decision-directed (DD) error upon receipt of the corrected signal from the first means;
- third means for calculating a Sato error upon receipt of the corrected signal from the first means;
- fourth means for taking the absolute value of a real part and an imaginary part of the DD error calculated from the second means, and summing the absolute value of the real part and the absolute value of the imaginary part of the DD error to obtain a sum;
- fifth means for multiplying the Sato error output from the third means by a first scale constant;
- and
- sixth means for multiplying a resultant output of the fifth means by the sum output from the fourth means.
Dependencies are inferred from the claim text.