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US 7,068,713 B2Granted
Digital filter circuit
AssigneeNEC Corporation
InventorMotoya Iwasaki
Life of this patent
Estimating the term…
Abstract
A digital filter circuit includes a decoder, ROM tables, multipliers, and an adder. The decoder decomposes an input multilevel signal into a plurality of 1-bit signals. The ROM tables output filter waveforms stored in advance, on the basis of the 1-bit signals output from the decoder. The multipliers and adder execute a plurality of weighting operations for the respective bits of outputs from the ROM tables and then add the outputs.
Claims7
A digital filter circuit comprising:
- decoding means for decomposing an input multilevel signal into a plurality of 1-bit signals;
- a plurality of ROM tables which output filter waveforms stored in advance, on the basis of the 1-bit signals output from said decoding means;
- and
- weighting and addition means for executing a plurality of weighting operations for respective bits of outputs from said ROM tables and then adding the outputs.
1 more element
A digital filter circuit comprising:
- a decoder which decomposes an input multilevel signal containing a plurality of bits into 1-bit signals and outputs the 1-bit signals;
- a plurality of shift registers which receives the 1-bit signals from said decoder;
- a counter which counts input sample clocks and outputs count values;
- a plurality of ROM tables which output filter waveforms that are stored in advance and correspond to input data sequences on the basis of the outputs from said shift registers and counter;
- multipliers which weight respective bits of outputs from said ROM tables in correspondence with the bit outputs from said decoder;
- and
- an adder which adds the outputs from said multipliers.
4 more elements
Dependencies are inferred from the claim text.