Circuit and method for processing communication packets and valid data bytes

A method for processing data packets within a communication system, the method comprising:

• receiving a first data packet in the communication system, the first packet ending with a valid byte and an invalid byte of data;
• dropping the invalid byte of data;
• receiving a second data packet that begins with a first valid byte of data;
• and
• concatenating the valid byte of the first data packet with the first valid byte of the second data packet.

A concatenation circuitry, comprising:

• a first multiplexing logic circuitry having a data output port, a data select port, and first and second data input ports, the data select port for selectively coupling any one of the first, or second data input ports to the data output port;
• a first register, having a data input port for receiving input data and a data output port for coupling to the first data input port of the multiplexing logic circuitry;
• a second register having a data input port for receiving input data, and for coupling to the data input port of the first register, the second register having a data output port for coupling to the second data input port of the multiplexing logic circuitry;
• a third register having a data input port for coupling to the data output port of the first multiplexing logic circuitry, and a data output port for outputting data;
• a fourth register having a data input port, and a data output port for outputting data;
• and
• a second multiplexing logic circuitry having a first data input port for coupling to the data output port of the second register, the second multiplexing logic circuitry having a second data input port for coupling to the input port of the second register, the second multiplexing logic circuitry having a data output port for coupling to the data input port of the fourth register, the second multiplexing logic circuitry having a data select port for selectively coupling either the first data input port or the second data input port with the data output port of the second multiplexing logic circuitry.

A logic circuitry for processing data packets within a communication system such that data packets contain valid bytes of data, the circuitry comprising:

• logic circuitry for determining that a first packet ends with a valid byte and an invalid byte of data;
• logic circuitry for dropping the invalid byte of data;
• logic circuitry for determining that a second data packet that begins with a valid byte of data;
• and
• logic circuitry for concatenating the valid byte of the first data packet with the valid byte of the second data packet.

A circuit for processing packets of data wherein a packet includes one or more words each having a first byte and a second byte, the circuit comprising:

• a first register coupled to receive and store the first byte of each word;
• a second register coupled to receive and store the second byte of each word;
• a third register coupled to the first register and configured to receive and store contents of the first register in response to a clock signal;
• a fourth register coupled to the second register and configured to receive and store contents of the second register in response to the clock signal;
• and
• a multiplexing circuit coupled to the third and fourth registers and configured to selectively rearrange pairing of bytes.