Data packet switching node accommodating very high bit rate interfaces

A data packet switching node to be used in an asynchronous digital network, comprising:

• an input stage, cutting data packets into segments of constant length;
• a switching matrix for switching, said switching matrix having input ports and output ports supporting identical bit rates B;
• a buffer memory for storing segments of a packet received at said input stage, wherein a memory location for storing segments is based on a clock period as measured from receipt of an initial segment and the modulo of the number of input ports of said switching matrix;
• and
• an output stage reconstructing said data packets from said segments supplied by said output ports of said switching matrix;
• wherein
• said input stage comprises at least one input interface with a bit rate equal to a multiple of B, ki*B, and means for splitting data packets received on said interface into segments distributed to ki input ports of said switching matrix;
• said output stage comprises at least one output interface with a bit rate equal to a multiple of B, ko*B, and means for reconstructing a data packet with a bit rate equal to ko*B by concatenating segments supplied by ko output ports of said switching matrix;
• and
• ki*ko>1.

A method for operating a data packet switching node comprising a switching matrix having input ports and output ports supporting identical bit rates B, an input stage comprising at least one input interface with a bit rate equal to a multiple of B, and an output stage comprising at least one output interface with a bit rate equal to a multiple of B, said method comprising:

• cutting input data packets into segments of constant length;
• distributing split data packets to ki input ports of said switching matrix;
• switching segments within said switching matrix;
• and
• reconstructing a data packet by concatenating segments supplied by ko output ports of said switching matrix, wherein ki*ko>1.