Data output controller in semiconductor memory device and control method thereof
AssigneeHynix Semiconductor Inc.
InventorHyun Woo Lee
Life of this patent
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Abstract
A data output controller of a high-speed memory device and a method therefor. The data output controller includes a first section for detecting a unit delay multiple of an external clock signal based on the external clock signal and a delay circuit of the external clock signal, a second section for analyzing data in an information storage unit, in which an internal timing is defined, by using values detected by the first section, and a third section for adjusting a data output timing in accordance with predetermined CAS latency based on analyzed values obtained through the second section. The data output controller to indicate an optimal point of a data output indicated by CAS latency information.
Claims8
A data output controller of a semiconductor device, the data output controller comprising:
- a delay unit for delaying an external clock signal;
- a delay line for delaying an output signal of the delay unit;
- a phase detector for detecting a differential phase between the external clock signal and an output signal of the delay line;
- a clock counter/delay line control unit for outputting a counter signal capable of controlling a time delay of the delay line in response to an output signal of the phase detector;
- a timing decoder/register for checking frequency of the external clock signal in response to an output signal of the clock counter/delay line control unit and storing information related to the frequency;
- and
- a multiplexer for receiving a plurality of output enable control signals, wherein the multiplexer selects one of output enable control signals according to the frequency information of the external clock signal which is checked by the timing decoder/register, and the output enable control signals include CAS latency of the semiconductor memory device and control an operation of an output driver of the semiconductor memory device.
A data output controller of a semiconductor device, the data output controller comprising:
- a first means for detecting a unit delay multiple of an external clock signal based on the external clock signal and a delay circuit of the external clock signal;
- a second means for analyzing data in an information storage unit, in which an internal timing is defined, by using values detected by the first means;
- and
- a third means for adjusting a data output timing in accordance with predetermined CAS latency based on analyzed values obtained through the second means.
Dependencies are inferred from the claim text.