Clock control in sequential circuit for low-power operation and circuit conversion to low-power sequential circuit

A memory element which updates its content in synchronization with a supplied clock, comprising:

• a latch circuit which acquires a supplied signal when the supplied clock is changed to a first logic value and which retains the acquired signal as the content of the memory element when the supplied clock is changed to a second logic value;
• and a
• variation detection circuit which outputs a variation signal indicative of a variation occurred in the content of the memory element when the input and output of the latch circuit are different and the supplied clock is changed to the first logic value,
• wherein the output of the latch circuit is a first output;
• the variation signal output from the variation detection circuit is a second output;
• and the first and second outputs are outputs of the memory elements.

A circuit modifying method for obtaining connection information of a new sequential circuit based on connection information of an original sequential circuit including a plurality of memory elements, each of which updates its content in synchronization with a supplied clock, the plurality of memory elements including a memory element which functions as a master cell and a memory element which functions as a slave cell, an input to the slave cell being varied when a content of the master cell is varied, the method comprising:

• a slave cell extraction step of extracting the slave cell from connection information of the original sequential circuit;
• a master cell group extraction step of extracting, for each extracted slave cell, a master cell group which includes at least one master cell corresponding to the slave cell from the connection information of the original sequential circuit;
• a variation detection means generation step of generating connection information of variation detection means which outputs a variation signal when a content of any of the master cells included in the extracted master cell group is varied;
• a clock pulse generator generation step of determining a clock domain so as to include some of the extracted slave cells whose extracted master cell groups are common, extracting a clock which is to be input to the slave cells included in the clock domain from connection information of the original sequential circuit, and generating connection information of a clock pulse generator based on the extracted clock;
• and
• a connection information synthesizing step of synthesizing the connection information of the original sequential circuit, the connection information of the variation detection means which is generated at the variation detection means generation step, and the connection information of the clock pulse generator which is generated at the clock pulse generator generation step to obtain connection information of the new sequential circuit,
• wherein the clock pulse generator generates a clock pulse as the clock extracted at the clock pulse generator generation step based on a variation signal output from the variation detection means.

A circuit-designing support system for obtaining connection information of a new sequential circuit based on connection information of an original sequential circuit including a plurality of memory elements, each of which updates its content in synchronization with a supplied clock, the plurality of memory elements including a memory element which functions as a master cell and a memory element which functions as a slave cell, an input to the slave cell being varied when a content of the master cell is varied, the system comprising:

• slave cell extraction means for extracting the slave cell from connection information of the original sequential circuit;
• master cell group extraction means for extracting, for each extracted slave cell, a master cell group which includes at least one master cell corresponding to the slave cell from the connection information of the original sequential circuit;
• variation detection means-generation means for generating connection information of variation detection means which outputs a variation signal when a content of any of the master cells included in the extracted master cell group is varied;
• clock pulse generator generation means for determining a clock domain so as to include some of the extracted slave cells whose extracted master cell groups are common, extracting a clock which is to be input to the slave cells included in the clock domain from connection information of the original sequential circuit, and generating connection information of a clock pulse generator based on the extracted clock;
• and
• connection information synthesizing means for synthesizing the connection information of the original sequential circuit, the connection information of the variation detection means which is generated by the variation detection means-generation means, and the connection information of the clock pulse generator which is generated by the clock pulse generator generation means to obtain connection information of the new sequential circuit,
• wherein the clock pulse generator generates a clock pulse as the clock extracted by the clock pulse generator generation means based on a variation signal output from the variation detection means.

A communication device comprising a semiconductor integrated circuit, wherein the semiconductor integrated circuit comprises:

• a sequential circuit which includes a plurality of memory elements, each memory element updating its content in synchronization with a supplied clock, the plurality of memory elements including a memory element which functions as a master cell and a memory element which functions as a slave cell, an input to the slave cell being varied when a content of the master cell is varied, wherein the sequential circuit includes:
• variation detection means which outputs a variation signal when the content of the master cell is varied;
• and
• a clock pulse generator for generating a clock pulse based on the variation signal and supplying the clock pulse to the slave cell as the supplied clock.

An information reproducing device comprising a semiconductor integrated circuit, wherein the semiconductor integrated circuit comprises:

• a sequential circuit which includes a plurality of memory elements, each memory element updating its content in synchronization with a supplied clock, the plurality of memory elements including a memory element which functions as a master cell and a memory element which functions as a slave cell, an input to the slave cell being varied when a content of the master cell is varied, wherein the sequential circuit includes:
• variation detection means which outputs a variation signal when the content of the master cell is varied;
• and
• a clock pulse generator for generating a clock pulse based on the variation signal and supplying the clock pulse to the slave cell as the supplied clock.

An image display device comprising a semiconductor integrated circuit, wherein the semiconductor integrated circuit comprises:

• a sequential circuit which includes a plurality of memory elements, each memory element updating its content in synchronization with a supplied clock, the plurality of memory elements including a memory element which functions as a master cell and a memory element which functions as a slave cell, an input to the slave cell being varied when a content of the master cell is varied, wherein the sequential circuit includes:
• variation detection means which outputs a variation signal when the content of the master cell is varied;
• and
• a clock pulse generator for generating a clock pulse based on the variation signal and supplying the clock pulse to the slave cell as the supplied clock.

An electronic device comprising a semiconductor integrated circuit, wherein the semiconductor integrated circuit comprises:

• a sequential circuit which includes a plurality of memory elements, each memory element updating its content in synchronization with a supplied clock, the plurality of memory elements including a memory element which functions as a master cell and a memory element which functions as a slave cell, an input to the slave cell being varied when a content of the master cell is varied, wherein the sequential circuit includes:
• variation detection means which outputs a variation signal when the content of the master cell is varied;
• and
• a clock pulse generator for generating a clock pulse based on the variation signal and supplying the clock pulse to the slave cell as the supplied clock.

An electronic controller comprising a semiconductor integrated circuit, wherein the semiconductor integrated circuit comprises:

• a sequential circuit which includes a plurality of memory elements, each memory element updating its content in synchronization with a supplied clock, the plurality of memory elements including a memory element which functions as a master cell and a memory element which functions as a slave cell, an input to the slave cell being varied when a content of the master cell is varied, wherein the sequential circuit includes:
• variation detection means which outputs a variation signal when the content of the master cell is varied;
• and
• a clock pulse generator for generating a clock pulse based on the variation signal and supplying the clock pulse to the slave cell as the supplied clock.

A movable apparatus comprising an electronic controller, wherein the electronic controller comprises a semiconductor integrated circuit, and wherein the semiconductor integrated circuit comprises:

• a sequential circuit which includes a plurality of memory elements, each memory element updating its content in synchronization with a supplied clock, the plurality of memory elements including a memory element which functions as a master cell and a memory element which functions as a slave cell, an input to the slave cell being varied when a content of the master cell is varied, wherein the sequential circuit includes:
• variation detection means which outputs a variation signal when the content of the master cell is varied;
• and
• a clock pulse generator for generating a clock pulse based on the variation signal and supplying the clock pulse to the slave cell as the supplied clock.