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US 7,068,564 B2Granted
Timer lockout circuit for synchronous applications
AssigneeInternational Business Machines Corporation
InventorsMark D Jacunski, Alan D Norris, Samuel K Weinstein
Life of this patent
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Abstract
A SDRAM mid a tinier lockout circuit. The SDRAM including: at least one bank of DRAM cells; the SDRAM operable to a first specification defined by a first clock frequency, a first write recovery time and a first time interval for precharge to row address strobe; and a circuit for programming the SDRAM operable to a second specification defined by a second clock frequency, a second write recovery time and a second time interval for precharge to row address strobe.
Claims20
A SDRAM, comprising:
- at least one bank of DRAM cells;
- said SDRAM operable to a first specification defined by a first clock frequency, a first write recovery time and a first time interval for precharge to row address strobe;
- means for programming said SDRAM operable to a second specification defined by a second clock frequency, a second write recovery time and a second time interval for precharge to row address strobe;
- and
- wherein precharging of bitlines in said at least one bank of DRAM cells is delayed by a time interval substantially equal to the difference between said first write recovery time and said second write recovery time.
2 more elements
A SDRAM comprising:
- at least one bank of DRAM coils;
- said SDRAM operable to a first write recovery time;
- a first circuit for programming said SDRAM operable to a second write recovery time;
- and
- a second circuit for delaying the start of a precharge command for a time interval equal to said first write recovery time when said SDRAM is operable to said second write recovery time.
2 more elements
A SDRAM comprising:
- at least one bank of DRAM cells;
- said SDRAM operable to a first specification defined by a first clock frequency, a first write recovery time and a first time interval for precharge to row address strobe;
- said SDRAM operable to a second specification defined by a second clock frequency, a second write recovery time and a second time interval for precharge to row address strobe;
- a programmable circuit adapted to control operation of said SDRAM based on said first and said second write recovery times;
- wherein precharging of bitlines in said at least one bank of DRAM cells is delayed by a time interval substantially equal to the difference between said first write recovery time and said second write recovery time.
2 more elements
Dependencies are inferred from the claim text.