Compact decode and multiplexing circuitry for a multi-port memory having a common memory interface
AssigneeMicron Technology, Inc.
InventorsAlistair Gratrex, Graham Kirsch
Life of this patent
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Abstract
A memory array for a multi-port memory having a common memory interface and a plurality of memory ports through which the memory array is accessed is provided. The memory array includes (r•s•t) memory locations with the memory array organized as a first memory sub-array accessible through a first of the plurality of memory ports as a (m×t) memory array and organized as a second memory sub-array accessible through a second of the plurality of memory ports as a (n×t) memory array. Both m and n are multiples of a value r, and the sum of (m/r) and (n/r) is equal to s. The memory array further organized as a common memory array accessible through the common memory interface as a (r×s×t) memory array.
Claims5
A method for accessing a multi-port memory having a common memory interface and a plurality of memory ports, the method comprising:
- decoding first address signals for accessing memory cells of a first memory array of the multi-port memory;
- coupling data between the first memory cell array and a first one of the plurality of memory ports in response to accessing memory cells of the first memory cell array through the first one of the plurality of memory ports;
- decoding second address signals for accessing memory cells of a second memory array of the multi-port memory;
- coupling data between the second memory cell array and a second one of the plurality of memory ports in response to accessing memory cells of the second memory cell array through the second one of the plurality of memory ports;
- decoding third address signals for accessing memory cells of the first or second memory cell array, the number of third address signals decoded for accessing memory cells of the first memory cell array the same as for accessing memory cells of the second memory cell array through the common memory interface;
- and
- coupling data between memory cells of the first or second memory cells array and the common memory interface in response to accessing memory cells of the first or second memory cell array through the common memory interface.
Dependencies are inferred from the claim text.