US 7,068,562 B2Granted

Semiconductor device with non-volatile memory and random access memory

AssigneeRenesas Technology Corp.

InventorsSeiji Miura, Kazushige Ayukawa

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Abstract

A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.

Claims20

Dependent claims

A memory module mounted in a package, comprising:

a non-volatile memory;
a random access memory;
a controller controlling the non-volatile memory and the random access memory;
a controller controlling the non-volatile memory and the random access memory;
a command register written an instruction code;
a plurality of external command signal terminals;
a plurality of external address terminals;
and
a plurality of external data terminals, wherein the controller reads out data from the non-volatile memory and writes the data read out from the non-volatile memory to the random access memory when a load instruction code is written into the command register, wherein
when command signals inputted to the plurality of command signal terminals indicate a write operation and address signal inputted to the plurality of external address terminals indicate an access to the command register, the load instruction code is written into the command register via the plurality of external data terminals, and
when command signals inputted the plurality of command signal terminals indicate the write operation and address signal inputted to the plurality of external address terminals indicates an access to the random access memory, data inputted to the plurality of external data terminals is written into the random access memory.

8 more elements

A memory module, comprising:

a non-volatile memory;
a random access memory;
a command register;
a plurality of external command terminals;
a plurality of external address terminals;
and
a plurality of external data terminals, wherein
the memory module transfers data from the non-volatile memory to the random access memory in a load operation,
the load operation starts by writing a load instruction code to the command register,
the load instruction code is written into the command register via the plurality of external data terminals when command signals which indicate a write operation are inputted from the plurality of external command terminals and address signals which indicate an access to the command register is inputted from the plurality of external address terminals, and
the memory module writes data inputted to the plurality of external data terminals to the random access memory when command signals which indicate the write operation are inputted from the plurality of external command terminals and address signals which indicate an access to the random access memory are inputted from the plurality of external address terminals.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/152,526Filed 13 Jun 2005 · continuation
Priority: JP 2001-17497811 Jun 2001
Published: US 2005/0232059 A120 Oct 2005
Granted: 27 Jun 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

G06F 12/0246
Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory: in block erasable memory, e.g. flash memory
G11C 5/02
Details of stores covered by group G11C11/00: disposition of storage elements, e.g. in the form of a matrix array
G11C 5/025
Disposition of storage elements, e.g. in the form of a matrix array: geometric lay-out considerations of storage- and peripheral-blocks in a…
G11C 5/04
Disposition of storage elements, e.g. in the form of a matrix array: supports for storage elements , e.g. memory modules; Mounting or fixing of…

Family

Application10/164,905Parent of this continuation · filed 10 Jun 2002
Application10/861,452Parent of this continuation · filed 7 Jun 2004
US 2005/0232059 A1Pre-grant publication · published 20 Oct 2005
US 6,952,368 B2Parent of this continuation
US 6,791,877 B2Parent of this continuation
US 2002/0185337 A1Published application
US 2004/0223366 A1Published application
US 7,068,562 B2This patent

From the US filing history. Foreign family members aren’t listed.