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US 7,068,560 B2Granted
High speed low voltage driver
AssigneeMicron Technology, Inc.
InventorsEbrahim Abedifard, Frankie Fariborz Roohparvar
Life of this patent
Estimating the term…
Abstract
A high speed high and low voltage driver provides an output voltage without taxing a pumped voltage. The pumped voltage is used only when the output node has risen substantially to a supply voltage without draining the pumped voltage.
Claims23
A processing system, comprising:
- a processor;
- and
- a memory coupled to the processor to store data provided by the processor and to provide data to the processor, the memory comprising:
- an array of memory cells;
- control circuitry to read, write and erase the memory cells;
- address circuitry to latch address signals provided on address input connections;
- and
- a driver for the array, comprising:
- an enable circuit providing an enable signal;
- a pull down transistor having its gate connected to the enable signal, to ground an output node when the enable signal is disabled;
- a pass transistor having its gate connected through a first p-type pull-up transistor connected between a pumped voltage and the gate of the pass transistor;
- an inverter connected between the enable circuit output and the pass transistor;
- a second pull down transistor connected between ground and the gate of the pass transistor;
- a series connection of two inverters connected between the output of the first inverter and the gate of the second pull down transistor;
- and
- a second p-type transistor connected between the pumped voltage and the output node, the gate of the second p-type transistor connected to the gate of the pass transistor.
13 more elements
A processing system, comprising:
- a processor;
- and
- a memory coupled to the processor to store data provided by the processor and to provide data to the processor, the memory comprising:
- an array of memory cells;
- control circuitry, including a pass transistor block to control access to the memory during an active cycle, to read, write and erase the memory cells;
- and
- a driver circuit to control operation of the pass transistor block, the driver circuit comprising:
- a first path for providing a supply voltage to an output node upon initiation of a read cycle;
- and
- a second path for providing a pumped voltage above the supply
- voltage after providing the supply voltage.
8 more elements
A processing system, comprising:
- a processor;
- and
- a flash memory device coupled to the processor to store data provided by the processor and to provide data to the processor, the memory comprising:
- an array of floating gate memory cells;
- and
- control circuitry to read, write and erase the floating gate memory cells;
- and
- a driver circuit to control read access, the driver circuit comprising:
- a NAND gate providing a read signal;
- a pull down transistor having its gate connected to the read signal, to ground an output node when the read signal is disabled;
- a pass transistor having its gate connected through a first p-type pull-up transistor connected between a pumped voltage and the gate of the pass transistor;
- an inverter connected between the NAND gate output and the pass transistor;
- a second pull down transistor connected between ground and the gate of the pass transistor;
- a series connection of two inverters connected between the output of the first inverter and the gate of the second pull down transistor;
- and
- a second p-type transistor connected between the pumped voltage and the output node, the gate of the second p-type transistor connected to the gate of the pass transistor.
13 more elements
A processing system, comprising:
- a processor;
- and
- a memory coupled to the processor to store data provided by the processor and to provide data to the processor, the memory comprising:
- an array of memory cells;
- control circuitry, including a pass transistor block to control access to the memory during an active cycle, to read, write and erase the memory cells;
- and
- a circuit for providing an output voltage at an output node to selectively control a gate of a pass transistor of the pass transistor block, the circuit comprising:
- first and second branches, the first branch coupled to the output node to raise a potential at the output node to approximately a supply voltage, and the second branch coupled to the output node once the output node voltage has reached a predetermined potential threshold, to raise the potential of the output node above the threshold using a pumped voltage.
5 more elements
Dependencies are inferred from the claim text.