Word line enable timing determination circuit of a memory device and methods of determining word line enable timing in the memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsHyun-Suk Lee, Kyung-Woo Nam
Life of this patent
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Abstract
A word line enable timing determination circuit of a memory device and method of determining word line enable timing in a memory device may be configured to adjust enable timing at which to activate a word line for at least one read/write command input to the memory device. This may be based on whether the memory device is performing a hidden refresh operation. In an example, and when a read/write command is input to the memory device, a word line for the read/write command may be activated after a first delay if the memory device is not executing a hidden refresh operation. Otherwise, a word line for the read/write command is activated after a second delay.
Claims28
A word line enable timing determination circuit in a memory device adapted to perform a hidden refresh operation, comprising:
- a detector detecting an address signal and generating a detection pulse (PP) signal in response thereto;
- a first signal generator generating a delayed detection pulse signal (PUL) having a first pulse width;
- a second signal generator generating a pulse signal (PULP) based on the state of the PUL;
- a third signal generator generating a refresh cutting signal (NERFH) in response to a delayed version of at least one of the PUL and PULP;
- a fourth signal generator generating a refresh pulse signal (SRFHP) in response to an output from an internal refresh oscillator, and cutting off the SRFHP in response to the NERFH;
- a first circuit generating a word line duration signal (PWL) in response to the PULP and the SRFHP;
- and
- a second circuit for extending the first pulse width of the PUL to a second pulse width in response to the PWL.
A method of determining word line enable timing in a memory device adapted to perform a hidden refresh operation, comprising:
- when a read/write command is input to the memory device
- activating a word line for the read/write command after a first delay, if the memory device is not executing a hidden refresh operation, else
- activating a word line for the read/write command after a second delay.
A method of determining word line enable timing in a memory device, comprising:
- when consecutive first and second read/write commands are input to the memory device, and
- if the second read/write command is received by the memory device within a first time after receiving a first read/write command
- ignoring the first read/write command;
- and
- activating a word line for the second read/write command after the first time, else
- if receiving the second read/write command within a time duration that is greater than the first time but less than a duration of a row cycle time (trc) after receiving the first read/write command
- activating a word line for the first read/write command, and
- activating a word line for the second read/write command, after a second time has elapsed.
A method of determining word line enable timing in a memory device, comprising:
- when consecutive first, second and third read/write commands are input to the memory device,
- if the second read/write command is received by the memory device within a time duration that is greater than a first time but less than a duration of a row cycle time (trc) after receiving the first read/write command, and the third read/write command is received after receiving the second read/write command in a time duration that is less than or equal to the first time,
- activating a word line for the first read/write command,
- ignoring the second read/write command, and
- activating a word line for the third read/write command.
A method of determining word line enable timing in a memory device, comprising:
- adjusting enable timing at which to activate a word line for a memory cell of the memory device in response to at least one read/write command input to the memory device based on whether the device is performing a hidden refresh operation.
Dependencies are inferred from the claim text.