Semiconductor memory device having row path control circuit and operating method thereof

A semiconductor memory device, comprising:

• a memory array block having a number of unit memory cells;
• command decoding means for receiving external commands to generate a read signal, a write signal, a bank signal, an active signal and a refresh signal;
• selecting signal generating means for generating a selecting signal to select an activation scheme for a word line in a cycle;
• bank controlling means for adjusting activation time points of a first bank driving signal and a second bank driving signal in response to the selecting signal;
• internal address counting means for generating an internal address in response to the refresh signal;
• row address latching means for selecting one of the internal address and an inputted address to output as a row address;
• first decoding means for decoding the row address in response to the first bank driving signal to activate a word line in the memory array block;
• second decoding means for decoding the row address in response to the second bank driving signal to activate a word line in the memory array block;
• first row controlling means for activating a first sense amplifier enable signal in response to the first bank driving signal;
• second row controlling means for activating a second sense amplifier enable signal in response to the second bank driving signal;
• and
• a sense amplifying block for sensing and amplifying memory cell data in the activated word line in response to the first sense amplifier enable signal and the second sense amplifier enable signal.

A driving method for performing a refresh cycle in a semiconductor memory device, comprising the steps of:

• (a) activating a refresh signal in response to input of external commands;
• (b) activating a bank signal in response to the refresh signal and generating an internal address;
• (c) activating a first bank driving signal in response to the bank signal and activating a second bank driving signal after a delay;
• (d) activating a word line corresponding to the internal address in response to the first bank driving signal;
• (e) activating a word line having an address as same as the activated word line but one particular bit;
• (f) deactivating the first bank driving signal in response to deactivation of the bank signal and deactivating the second bank driving signal after the delay;
• (g) deactivating the word line in response to the deactivation of the first bank driving signal;
• and
• (h) deactivating the other word line in response to the deactivation of the second bank driving signal.

A driving method for performing a refresh cycle in a semiconductor memory device, comprising the steps of:

• (a) activating a refresh signal in response to input of external commands;
• (b) activating a bank signal in response to the refresh signal and generating an internal address;
• (c) simultaneously activating a first bank driving signal and a second bank driving signal in response to the bank signal;
• (d) simultaneously activating two word lines corresponding to the internal address and having the respective addresses that are equal to each other except for a particular bit in response to the first bank driving signal and the second bank driving signal;
• (e) deactivating the first bank driving signal and the second bank driving signal in response to deactivation of the bank signal;
• and
• (f) deactivating the two word lines in response to the deactivation of the first bank driving signal and the second bank driving signal.

A semiconductor memory device, comprising:

• a bank having a number of unit memory cells;
• command decoding means for generating a bank signal and a refresh signal in response to external commands;
• bank controlling means for driving the bank in response to the bank signal and the refresh signal to output a first bank driving signal and a second bank driving signal;
• first decoding means for driving a plurality of first rows in the bank in response to the first bank driving signal;
• and
• second decoding means for driving a plurality second rows in the bank in response to the second bank driving signal,
• wherein the bank controlling means adjusts the enable time points of the first and the second bank driving signals in response to input of a selecting signal that corresponds to an activation scheme for the word line in a cycle.