Semiconductor memory storage device and a redundancy control method therefor

A semiconductor memory device comprising:

• a plurality of bit lines each of which is connected to a plurality of memory cells, at least one of bit lines is connected to at least one redundant memory cell(s);
• and
• a bias voltage supply section for supplying high bias voltage to memory cells or/and redundant memory cells through bit line depending on length of the bit line, wherein, in the case where redundancy processing is not conducted, the bias voltage supply section supplies a bias voltage value based on address information which indicates a connection point of bit line and memory cell and in the case where redundancy processing is conducted, defruiting of the address information is executed in accordance with a redundancy select signal and the bias voltage supply section supplies a bias voltage value based on length of bit line reaching redundant memory cell.

A redundancy control method for a semiconductor memory device comprising a plurality of bit lines each of which is connected to a plurality of memory cells, at least one of bit lines is connected to at least one redundant memory cell(s), for supplying bias voltage to memory cells or/and redundant memory cells through bit line, the redundancy control method comprising the steps of:

• a first voltage adjust step for adjusting bias voltage to high level in accordance with address information corresponding to length of bit line reaching memory cell, namely, a connection point of bit line and memory cell, in case redundancy processing is not conducted;
• and
• a second voltage adjust step for adjusting bias voltage to high level in accordance with a redundancy select signal corresponding to length of bit line reaching memory cell instead of the address information in case redundancy processing is conducted.