Apparatus and method for implementing multiple memory redundancy with delay tracking clock

A memory redundancy control apparatus, comprising:

• a plurality of compare stages, each compare stage configured to compare bits of a requested memory address to fuse information bits corresponding to one of a plurality of defective memory address;
• each compare stage further comprising a static exclusive OR (XOR) block for each bit in said memory address, said static XOR blocks configured to compare an individual bit of said requested memory address with an individual fuse information bit, with outputs of said static XOR blocks inputted to a dynamic NOR stage for each of said defective memory addresses;
• each dynamic NOR stage having a precharged output so as to initially deactivate primary subarray decoding circuitry, said dynamic NOR stages further triggered by a clock signal thereto;
• upon activation of said clock signal, the output of a given dynamic NOR stage remains precharged whenever a match exists between said requested memory address and the defective memory address corresponding to the given dynamic NOR stage, and the output of the given dynamic NOR stage is discharged whenever a mismatch exists between said requested memory address and said defective memory address;
• and
• a delay tracking clock generator configured to generate a delay tracking clock signal with respect to said dynamic NOR stages, said delay tracking clock signal configured to gate the outputs of said dynamic NOR stages to spare subarray decoding circuitry, wherein said spare subarray decoding circuitry is activated whenever any of the outputs of said dynamic stages remains precharged following activation of said clock signal.

A method for implementing memory redundancy control, the method comprising:

• configuring a plurality of compare stages to compare bits of a requested memory address to fuse information bits corresponding to one of a plurality of defective memory address;
• each compare stage further comprising a static exclusive OR (XOR) block for each bit in said memory address, said static XOR blocks configured to compare an individual bit of said requested memory address with an individual fuse information bit, with outputs of said static XOR blocks inputted to a dynamic NOR stage for each of said defective memory addresses;
• each dynamic NOR stage having a precharged output so as to initially deactivate primary subarray decoding circuitry, said dynamic NOR stages further triggered by a clock signal thereto;
• upon activation of said clock signal, the output of a given dynamic NOR stage remains precharged whenever a match exists between said requested memory address and the defective memory address corresponding to the given dynamic NOR stage, and the output of the given dynamic NOR stage is discharged whenever a mismatch exists between said requested memory address and said defective memory address;
• and
• configuring a delay tracking clock generator to generate a delay tracking clock signal with respect to said dynamic NOR stages, said delay tracking clock signal configured to gate the outputs of said dynamic NOR stages to spare subarray decoding circuitry, wherein said spare subarray decoding circuitry is activated whenever any of the outputs of said dynamic stages remains precharged following activation of said clock signal.