Semiconductor integrated circuit with noise reduction circuit
AssigneeFujitsu Limited
InventorsHiroyuki Nakamoto, Kunihiko Gotoh
Life of this patent
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Abstract
A semiconductor integrated circuit includes a substrate, a digital circuit formed on a triple well formed in the substrate, a first node configured to supply a well potential of the digital circuit, a second node separate from the first node, and a substrate-potential supplying circuit, formed on the substrate, having an input node to receive an input potential from the second node and an output node to supply a substrate potential to the substrate, the substrate-potential supplying circuit having no direct-current path into which a direct current substantially flows through the input node, and configured to generate at the output node an output potential following the input potential.
Claims10
A semiconductor integrated circuit, comprising:
- a substrate;
- a digital circuit formed on a triple well formed in said substrate;
- a first node configured to supply a well potential of said digital circuit;
- a second node separate from said first node;
- and
- a substrate-potential supplying circuit, formed on said substrate, having an input node to receive an input potential from said second node and an output node to stabilize a substrate potential of said substrate, said substrate-potential supplying circuit having no direct-current path into which a direct current substantially flows through said input node, and configured to generate at said output node an output potential following the input potential.
A semiconductor integrated circuit, comprising:
- a substrate;
- a digital circuit formed on a triple well formed in said substrate;
- a first node configured to supply a well potential of said digital circuit;
- a second node separate from said first node;
- and
- a substrate-potential supplying circuit, formed on said substrate, having an input node to receive an input potential from said second node and an output node to supply a substrate potential to said substrate, said substrate-potential supplying circuit having no direct-current path into which a direct current substantially flows through said input node, and configured to generate at said output node an output potential following the input potential, wherein said substrate-potential supplying circuit includes:
- a PMOS transistor having a gate node thereof coupled to said input node, a drain node thereof coupled to a ground potential, and a source node and back gate thereof coupled to said output node;
- and
- a current source coupled to said source node.
A semiconductor integrated circuit, comprising:
- a substrate;
- a digital circuit formed on a triple well formed in said substrate;
- a first node configured to supply a well potential of said digital circuit;
- a second node separate from said first node;
- and
- a substrate-potential supplying circuit, formed on said substrate, having an input node to receive an input potential from said second node and an output node to supply a substrate potential to said substrate, said substrate-potential supplying circuit having no direct-current path into which a direct current substantially flows through said input node, and configured to generate at said output node an output potential following the input potential, wherein said substrate-potential supplying circuit includes:
- a PMOS transistor having a gate node thereof coupled to said input node, a drain node thereof coupled to a ground potential, and a source node and back gate thereof coupled to said output node;
- a current source coupled to said source node of said PMOS transistor;
- an NMOS transistor having a gate node thereof coupled to said input node, a drain node thereof coupled to a power-supply potential, and a source node and back gate thereof coupled to said output node;
- and
- a current source coupled to said source node of said NMOS transistor.
A semiconductor integrated circuit, comprising:
- a substrate;
- a digital circuit formed on a triple well formed in said substrate;
- a first node configured to supply a well potential of said digital circuit;
- a second node separate from said first node;
- and
- a substrate-potential supplying circuit, formed on said substrate, having an input node to receive an input potential from said second node and an output node to supply a substrate potential to said substrate, said substrate-potential supplying circuit having no direct-current path into which a direct current substantially flows through said input node, and configured to generate at said output node an output potential following the input potential, wherein said substrate-potential supplying circuit includes:
- a transistor having a gate note thereof coupled to said input node and a source node thereof coupled to said output node;
- and
- a current source adapted to supply a current to said transistor.
Dependencies are inferred from the claim text.