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US 7,068,543 B2Granted
Flash memory
AssigneeMicron Technology, Inc.
InventorsAndrei Mihnea, Chun Chen
Life of this patent
Estimating the term…
Abstract
Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period.
Claims21
A flash memory, comprising:
- at least one floating-gate memory cell comprising a source, a drain, a control gate, a floating gate and a substrate;
- a memory control circuit for controlling operations on the at least one floating-gate memory cell;
- a wordline coupled to the control gate of the at least one memory cell;
- and
- a wordline drive transistor coupled to the wordline;
- wherein the memory control circuit is adapted to apply a voltage of a first polarity relative a common voltage to the control gate of the at least one floating-gate memory cell beginning substantially concurrently with applying a voltage of a second polarity relative the common voltage to the source of the at least one floating-gate memory cell;
- and
- wherein the memory control circuit is further adapted to begin discharging the voltage of the second polarity while allowing the voltage of the first polarity to float, and discharging the voltage of the first polarity at least two microseconds after beginning to discharge the voltage of the second polarity.
5 more elements
A flash memory, comprising:
- at least one floating-gate memory cell comprising a source, a drain, a control gate, a floating gate and a substrate;
- a memory control circuit for controlling operations on the at least one floating-gate memory cell;
- a wordline coupled to the control gate of the at least one memory cell;
- and
- a wordline drive transistor coupled to the wordline and having a parasitic drain capacitance on the order of 1–10 fF;
- wherein the memory control circuit is adapted to apply a first voltage of a first polarity relative a common voltage to the control gate of the at least one floating-gate memory cell beginning substantially concurrently with applying a voltage of a second polarity relative the common voltage to the source of the at least one floating-gate memory cell;
- and
- wherein the memory control circuit is further adapted to begin discharging the voltage of the second polarity at a rate sufficient to couple a second voltage of the first polarity to the control gate while allowing the first voltage of the first polarity to float, and discharging the first voltage of the first polarity at least two microseconds after beginning to discharge the voltage of the second polarity.
5 more elements
Dependencies are inferred from the claim text.