Phase-change memory device with overvoltage protection and method for protecting a phase-change memory device against overvoltages

A method for reading a phase-change memory device, comprising:

• providing a plurality of phase-change memory cells, arranged in rows and columns, said phase-change memory cells arranged on the same column being connected to a same bit line, and a plurality of first selectors, each coupled to a respective said phase-change memory cell;
• selectively addressing at least one of said bit lines, one of said first selectors, and the phase-change memory cell connected to the addressed bit line and to the addressed first selector;
• and
• supplying a bit line voltage to said addressed bit line wherein supplying said bit line voltage comprises regulating said bit line voltage on the basis of a first control voltage on said addressed first selector, coupled to said addressed phase-change memory cell.

A system comprising:

• a processor;
• a memory communicatively coupled to the processor, the memory comprising:
• a plurality of phase-change memory cells arranged in columns;
• a column decoder;
• and
• a biasing system including a plurality of reference selectors and configured to regulate a read voltage applied to a phase-change memory cell in the plurality of phase-change memory cells by controlling a current provided to a corresponding reference selector in the plurality of reference selectors.

A phase-change memory, comprising:

• a first phase-change memory cell including a first terminal and a second terminal;
• a first array selector including a third terminal and a fourth terminal wherein the third terminal is electrically coupled to the first terminal of the first phase-change memory cell;
• a first addressing line electrically coupled to the second terminal of the first phase-change memory cell;
• a second addressing line electrically coupled to the fourth terminal of the first array selector;
• and
• a biasing system including a first reference selector having a fifth terminal electrically coupled to the second addressing line, wherein the biasing system is configured to control a voltage applied across the first and second terminals of the first phase-change memory cell during a read operation of the first phase-change memory cell.

A phase-change memory comprising:

• a plurality of phase-change memory cells;
• means for reading a phase-change memory cell in the plurality of phase-change memory cells comprising an array selector;
• and
• means for controlling a voltage applied to a phase-change memory cell by the means for reading a phase-change memory cell comprising a corresponding reference selector.

A phase-change memory, comprising:

• a plurality of phase-change memory cells, arranged in rows and columns, said phase-change memory cells arranged on the same column being connected to a same bit line, and a plurality of first selectors, each coupled to a respective said phase-change memory cell;
• means for selectively addressing at least one of said bit lines, one of said first selectors, and the phase-change memory cell connected to the addressed bit line and to the addressed first selector;
• and
• means for supplying a bit line voltage to said addressed bit line configured to regulate said bit line voltage on the basis of a first control voltage on said addressed first selector, coupled to said addressed phase-change memory cell.