Resistive memory cell configuration and method for sensing resistance values

A method for sensing the resistance value of a selected resistive memory cell to be read, comprising:

• pretensioning of first current lines and a fourth current line to a predetermined first potential value;
• switching-on of a selection transistor being connected to a resistive memory cell to be read, while all remaining selection transistors are kept in their off-states;
• application of a predetermined second electrical potential having a potential difference as to the predetermined first potential on one of the first current lines being connected to the resistive memory cell to be read, while keeping all remaining first current lines and the fourth current line at the predetermined first potential value;
• and
• determination of the height of a current flowing through the fourth current line.

An array of resistive magnetic memory cells comprising:

• a plurality of first current lines;
• a plurality of second current lines;
• a plurality of third current lines;
• a plurality of magnetic memory cells being disposed in a memory matrix form between the first and second current lines, the first current lines defining the columns of the memory matrix, while the second current lines defining the rows of it, wherein each one of the magnetic memory cells being connected to one of the first current lines;
• a plurality of selection transistors having gates and drain-source paths, each drain-source path of the selection transistors being connected to a multiplicity of the magnetic memory cells of a row of the memory matrix, the drain-source paths of different selection transistors being connected to a fourth current line, the gates of the selection transistors of a row of the memory matrix form being connected to one of the third current lines;
• and
• a control circuit configured to sense a resistance of a selected memory cell by:
• pretensioning the plurality of first current lines and the fourth current line to a predetermined first potential value;
• switching on the selection transistor connected to the selected memory cell;
• applying a predetermined second potential value to the first current line connected to the selected memory cell the predetermined second potential value having a potential difference as to the predetermined first potential value;
• and
• determining a height of a sense current flowing through the fourth current line.

A method for sensing a resistance value of a selected memory cell, the method comprising:

• precharging bit lines and a sense line to a first potential value;
• turning on a selection transistor connected between a selected memory cell and the sense line;
• applying a second potential value to the bit line connected to the selected memory cell while maintaining the first potential value on the other bit lines, the second potential value greater than the first potential value;
• and
• sensing a resistance value of the selected memory cell based on a signal on the sense line.