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US 7,068,531 B2Granted
Bias-adjusted magnetoresistive devices for magnetic random access memory (MRAM) applications
AssigneeHoneywell International Inc.
InventorRomney R. Katti
Life of this patent
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Abstract
A method and apparatus are presented for shifting a hysteresis loop of a magnetoresistive device. For example, a method provides for applying a bias current to a word line of the magnetoresistive device during either a read sequence or a write sequence. The bias current is preferably configured to substantially center a hysteresis loop of the device without switching a binary state of the device.
Claims25
In a magnetoresistive memory device, a method comprising applying a bias current to a word line of the memory device to impose a bias field on a magnetoresistive element for centering a hysteresis loop of the magnetoresistive element.
A magnetoresistive device comprising:
- a magneloresistive element;
- a word line arranged near the magnetoresistive element for switching a state of the magnetoresistive element and for applying a bias field to the magnetoresistive element;
- a bias driver electrically connected to the word line for applying a bias current to the word line, the bias current being configured to impose a bias on the magnetoresistive element for centering a hysteresis loop of the magrietoresistive element, wherein the bias driver is configured to apply the bias current during a write cycle of the write driver, wherein the magnitude and direction of the bias current is configured to substantially limit a write hysteresis loop bias of the magnetoresistive element;
- and
- a write driver electrically connected to the word line for applying a switching current to the word line.
2 more elements
A magnetoresistive device comprising:
- a primary magnetoresistive element, wherein the primary magnetoresistive element is configured to switch between a first state with a low zero-field resistance and a second state with a high zero-field resistance when a magnetic field of sufficient strength is applied to the primary magnetoresistive element;
- a complementary magnetoresistive element, wherein the complementary magnetoresistive element is configured to switch between a first state with a high zero-field resistance and a second state with a low zero-field resistance when a magnetic field of sufficient strength is applied to the complementary magnetoresistive element;
- a primary bit line electrically connected to the primary magnetoresistive element;
- a complementary bit line electrically connected to the complementary magnetoresistive element;
- a word line electrically isolated from the primary magnetoresistive element and electrically isolated from the complementary magnetoresistive element, and wherein the word line is aligned near the primary magnetoresistive element and near the complementary magnetoresistive element, and wherein a current in the word line causes a magnetic field to be applied to the primary magnetoresistive element and to the complementary magnetoresistive element, and wherein the magnetic field applied to the primary magnetoresistive element is of the same magnitude but opposite sign to the magnetic field applied to the complementary magnetoresistive element;
- a bias driver electrically connected to the word line for generating a bias current in the word line;
- and
- a write driver electrically connected to the word line for generating a write current in the word line.
5 more elements
A magnetoresistive memory array comprising:
- a plurality of magnetoresistive memory cells arranged in rows and columns;
- a plurality of bit lines, wherein each bit line aligned in one row and coupled to each memory cell in the row;
- a plurality of word lines, wherein each word line is arranged near a column of memory cells, wherein a current passing through a word line creates a magnetic field acting along an easy axis of each of the memory cells in the column of memory cells;
- a write driver for generating a write current, wherein the output of the write driver is electrically connected to one or more of the plurality of word lines;
- and
- a bias driver, wherein the output of the bias driver is electrically connected to one or more of the plurality of word lines, the bias driver being configured to generate a bias current that substantially centers a biased hysteresis loop of a selected magnetoresistive memory cell.
3 more elements
Dependencies are inferred from the claim text.