US 7,068,529 B2 · Nonvolatile ferroelectric memory device

Abstract

The disclosed nonvolatile ferroelectric memory device comprises: a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of platelines, respectively; a read control block configured to convert the data level voltage stored in the memory cell into a corresponding data bit value of a plurality of data bit values and output the converted value externally; and a write control block configured to write a plurality of bit data inputted externally as a corresponding data level voltage of a plurality of data level voltages in the memory cell, wherein bitlines are layered into main bitline and sub-bitline by reducing a current value corresponding to a sensing voltage of the sub-bitline at an initial level of the main bit line. As a result, the FRAM can write a plurality of data levels in one ferroelectric memory cell.

Claims39

Dependent claims

A nonvolatile ferroelectric memory device which can read/write a plurality of data levels from/to ferroelectric memory cells including:

a control circuit block positioned in a middle of the memory device and configured to read/write data from/to the ferroelectric memory cells;
a data bus arranged between a plurality of memory cell arrays each comprising the ferroelectric memory cells wherein the data bus is positioned vertical to the control circuit block;
said control circuit block including,
a read control block configured to convert the data level voltage stored in the ferroelectric memory cell into a corresponding multi-bit data and output the multi-bit data externally;
and
a write control block configured to receive the multi-bit data inputted externally and write a corresponding voltage level to the multi-bit data into the ferroelectric memory cell.

3 more elements

A nonvolatile ferroelectric memory device comprising layered bitlines consisting of main bitline and sub-bitline, which can write and read a plurality of data levels in a ferroelectric memory cell by reducing a current value corresponding to a sensing voltage of the sub-bitline at an initial level of the main bit line, including:

a read control block configured to convert the data level voltage stored in the ferroelectric memory cell into a corresponding multi-bit data and output the multi bit data externally;
and a write control block configured to receive the multi-bit data inputted externally and write a corresponding voltage level to the multi-bit data into the ferroelectric memory cell;
said read control block including,
a sense amplifier array including a plurality of sense amplifiers configured to compare the data level voltage stored in the ferroelectric memory cell with a plurality of reference voltages, respectively, and output the comparison result;
a reference voltage generator array including a plurality of reference voltage generators configured to generate the plurality of reference voltages;
a data encoder configured to encode signals outputted from the plurality of sense amplifiers and output corresponding data;
said write control block including,
a data decoder configured to decode data inputted externally;
and
a digital-to-analog converter configured to generate a data level voltage corresponding to the data by using the decoded bit value.

7 more elements

Dependencies are inferred from the claim text.

Nonvolatile ferroelectric memory device

Life of this patent

Nonvolatile ferroelectric memory device

Life of this patent

Abstract

Claims39