Layout structure of bit line sense amplifier of semiconductor memory device

A layout method of a bit line sense amplifier of a semiconductor memory device having N piece of a bit line and a bit bar line comprising:

• arranging N piece of PMOS sense amplifier regions constituted with two PMOS transistors having a predetermined separation distance L in the bit line direction between gate regions;
• arranging N piece of NMOS sense amplifier regions constituted with two NMOS transistors where each gate region is apart as much as the same distance in the bit line direction from each gate region of the PMOS transistors;
• arranging 2N pieces of IO lines between the PMOS sense amplifier regions and the NMOS sense amplifier regions;
• and
• arranging 2N piece of IO switches for connecting gate regions of the PMOS and NMOS transistors with the IO lines through the bit lines and the bit bar lines, wherein the IO switches are connected to IO lines where a bit line direction distance between an IO switch connected to a bit line and an IO switch connected to the bit bar line is substantially equal to the separation distance L.

A layout structure of a sense amplifier comprising:

• N piece of bit line pairs structured by alternately arranging N piece of a bit line and N piece of a bit bar line in parallel with each other;
• N piece of IO line pairs arranged in a vertical direction relative to the bit line pair;
• N piece of PMOS sense amplifiers arranged in a left side/right side in comparison with the N piece of the IO line pairs, N piece of PMOS sense amplifiers structured by two PMOS transistors;
• N piece of NMOS sense amplifiers arranged in a left side/right side in comparison with the N piece of the IO line pairs, N piece of NMOS sense amplifiers structured by two PMOS transistors;
• 2N pieces of an IO switch including first, second and third terminals, wherein the first terminal is connected to one of a bit line or a bit bar line, and
• wherein the second terminal is connected to one of an IO line, and
• wherein the third terminal for switching between the first terminal and the second terminal is connected to a column selection line, wherein a difference ΔINGB-ΔING of a first distance ΔING from the first terminal of the IO switch connected to the bit line of one of bit line pair to a gate of the NMOS transistor and a second distance ΔINGB from the first terminal of the IO switch to the gate of the NMOS transistor is all same, and
• wherein the IO switch is connected to the bit line of one of the bit line pair, and the NMOS transistor is one of two NMOS transistors of the NMOS sense amplifier in the first distance, and
• wherein the IO switch is connected to the bit bar line of the bit line pair, and the NMOS transistor is one of the rest of two NMOS transistors of the sense amplifier in the second distance, and
• wherein the third terminal for switching between the first terminal and the second terminal is connected to a column selection line, wherein a difference ΔINGB-ΔING of a first distance ΔING from the first terminal of the IO switch connected to the bit line of one of bit line pair to a gate of the NMOS transistor and a second distance ΔINGB from the first terminal of the IO switch to the gate of the NMOS transistor is all same, and
• wherein the IO switch is connected to the bit line of one of the bit line pair, and the PMOS transistor is one of two PMOS transistors of the PMOS sense amplifier in the first distance, and
• wherein the IO switch is connected to the bit bar line of the bit line pair, and the PMOS transistor is one of the rest of two PMOS transistors of the sense amplifier in the second distance.