Method of operating multiple parallel-connected pulse-controlled inverters

Method of operating multiple (n) parallel-connected pulse-controlled inverters (1,2), wherein

• the individual current(s) of the (n) pulse-controlled inverters (1,2), or of a number reduced by 1(n−1) of pulse-controlled inverters (1,2) is/are regulated, and
• each pulse-controlled inverter (1,2) includes first (IGBTT11, IGBTT21) and second (IGBTT14, IGBTT24) insulated gate bipolar transistors and first (D11, D21) and second (D14, D24) diodes each connected in parallel with a respective one of the first (IGBTT11, IGBTT21) and second (IGBTT14, IGBTT24) insulated gate bipolar transistors in the direction of reverse voltage (UD−) to forward voltage (UD+),
• the input variable of regulation is generated by the difference between the setpoint value and the actual value of the corresponding output current, and by the modulation pattern, and
• for each pulse-controlled inverter (1, 2),
• when the actual value of current (I11, I21) is greater than the setpoint value, a turn-on edge of the first transistor (T11, T21) and turn-off edge of the second transistor (T14, T24) are each delayed, a turn-off edge of the first transistor (T11, T21) and turn-on edge the second transistor (T14, T24) remaining undelayed,
• when the actual value of the current (I11, I21) is smaller than the setpoint value, the turn-on edge of the first transistor (T11, T21) and turn-off edge of the second transistor (T14, T24) are undelayed, with the turn-off edge of the first transistor (T11, T21) and turn-on edge of the second transistor (T14, T24) each being delayed, and
• when the actual value of the current (I11, I21) equals the setpoint value, the turn-on edges and turn-off edges of the first (T11, T21) and second (T14, T24) transistors all remain undelayed.