Image processing apparatus
AssigneeSony Corporation
InventorAtsushi Narita
Life of this patent
Estimating the term…
Abstract
An image processing apparatus capable of performing a refresh operation without causing a drop in performance, an increase in cost, or damage to the apparatus. The apparatus further being capable of achieving a reduction in power consumption, and being provided with a memory I/F circuit able to not only refresh, for example, four DRAM modules simultaneously, but also capable of refreshing two DRAM modules at a same timing, then refreshing the remaining two DRAM modules simultaneously at a next timing, or refreshing the four DRAM modules one by one in order based on given refresh control data, and controlling the timing of the refresh operation for each divided DRAM module.
Claims13
An image processing apparatus comprising:
- a memory circuit divided into a plurality of memory modules and storing at least image data and requiring refreshing;
- a logic circuit for performing predetermined processing on the image data based on data stored in said memory circuit,
- said memory circuit and said logic circuit being accommodated on one semiconductor chip;
- and
- a refresh circuit that refreshes said memory circuit in units based on the number of said divided memory modules,
- wherein said memory circuit is divided into more than two memory modules,
- wherein each unit of the memory circuit includes memory modules that are located on opposite sides of the logic unit, and
- wherein the refresh circuit successively refreshes a plurality of memory modules in units of at least two memory modules when refresh control data given are first data, while it refreshes the plurality of memory modules one by one in a predetermined order when refresh control data given are second data.
An image processing apparatus comprising:
- a memory circuit divided into a plurality of memory modules storing at least image data and requiring refreshing;
- a logic circuit for performing predetermined processing on the image data based on data stored in said memory circuit,
- said memory circuit and said logic circuit being accommodated in one semiconductor chip, and
- said plurality of divided memory modules arranged at a periphery of said logic circuit;
- and
- a refresh circuit that refreshes said memory circuit in units based on the number of said divided memory modules,
- wherein each unit of the memory circuit includes memory modules that are located on opposite sides of the logic unit, and
- wherein the refresh circuit successively refreshes a plurality of memory modules in units of at least two memory modules when refresh control data given are first data, while it refreshes the plurality of memory modules one by one in a predetermined order when refresh control data given are second data.
Dependencies are inferred from the claim text.