System that facilitates reading multi-level data in non-volatile memory
AssigneeSpansion LLC
InventorsFatima Bathul, Darlene Hamilton, Eugen Gershon
Life of this patent
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Abstract
The present invention pertains to a system that facilitates a determination of the level of a bit in a dual sided ONO flash memory cell where each of the bits of the dual sided ONO flash memory cell can be programmed to multiple levels. One or more aspects of the present invention take into consideration the affect that the level of charge on one bit can have on the other bit, otherwise known as complimentary bit disturb. A metric known as transconductance is utilized in making the bit level determination to provide a greater degree of resolution and accuracy. In this manner, determining the bit level in accordance with one or more aspects of the present invention mitigates false or erroneous reads.
Claims15
An architecture adapted to determine a level of a bit in a multi-level memory cell, comprising:
- a current conversion component operative to convert a measured current from the cell into a corresponding analog voltage;
- an analog to digital (A/D) converter operative to convert the analog voltage into a digital value;
- and
- a data processor adapted to determine the level of the bit from the digital value, wherein the data processor is implemented as a field programmable gate array (FPGA), and wherein the FPGA comprises:
- a data vector processor operative to facilitate a determination of the level of the bit by comparing the digital value to predetermined criteria.
Dependencies are inferred from the claim text.