Architecture for an algorithmic analog-to-digital converter

A method for converting an input analog signal to an output digital bit stream, comprising:

• sampling and holding the input analog signal during a sample-and-hold clock period;
• generating N sets of bits during the sample-and-hold clock period using an ADC unit comprising one MDAC and one sub-ADC, wherein the N sets of bits are generated by alternately applying a residue or sampled voltage and a reference voltage to switched capacitors in the MDAC;
• and
• generating the output digital bit stream by adding the N sets of bits.

A method for converting an input analog signal to an output digital bit stream, comprising:

• a step for sampling and holding the input analog signal during a sample-and-hold clock period;
• a step for generating an ADC clock having N cycles per sample-and-hold clock period;
• a step for generating a new residue voltage per cycle using the sampled analog signal and previous residue voltages derived from the sampled analog signal;
• a step for generating a set of data bits per cycle from the new residue voltage;
• a step for generating feedback signals for generating the new residue voltage in the next cycle;
• and
• a step for generating the output digital bit stream using the N sets of data bits.

A system for conversion of an analog input signal to an output digital bit stream comprising:

• means for sampling and holding an input analog signal;
• means for applying the sampled and held signal to a switched capacitor circuit;
• means for generating a residue voltage with the switched capacitor circuit;
• means for generating N sets of data bits from the residue voltage per sampled and held signal;
• and
• means for generating feedback signals corresponding to the data bits to control reference voltages applied to the switched capacitor circuit, wherein the means for sampling and holding an input signal, means for applying the sampled and held signal to a switched capacitor circuit, and means for generating a residue voltage comprise a single operational amplifier.