Accurate sampling technique for ADC
AssigneeNational Semiconductor Corporation
InventorChristopher Alan Menkus
Life of this patent
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Abstract
A time interleaved ADC system includes a delay circuit that has a dynamically adjusted speed to achieve uniformly spaced sampling intervals. The adjustment control circuit monitors the sampling pulses associated with sampling time instant for each ADC, and provides one or more control signals to the delay circuit. In one example, the adjustment control circuit employs a phase detector circuit, an integrator circuit, and a dynamic biasing circuit. In this example, the phase detector circuit evaluates the sampling pulses to generate control signals for the integrator circuit, which generates signals that are utilized by the dynamic biasing circuit to adjust the delays associated with the delay circuit. The relative positions of the sampling pulses are controlled by adjusting the delay in the delay circuit.
Claims21
An apparatus for converting an analog input signal to a digital output signal, the apparatus comprising:
- a first analog-to-digital converter circuit that includes a first analog input port, a first sampling clock input port, and a first digital output port;
- a second analog-to-digital converter circuit that includes a second analog input port, a second sampling clock input port, and a second digital output port, wherein the first and second digital output ports are arranged to provide portions of the digital output signal in a time interleaved format when the first and second analog input ports are coupled to one another;
- an adjustment control circuit that is arranged to monitor sampling signals associated with the first and second analog-to-digital converter circuits, and also arranged to provide at least one control signal;
- and
- a clock driver circuit that is arranged to:
- receive an input clock signal, receive the at least one control signal, provide a first clock signal to the first sampling clock input port, and provide a second clock signal to the second sampling clock input port, wherein the clock driver circuit includes an adjustable delay circuit that is responsive to the at least one control signal.
A method of adjusting sampling clock intervals, comprising:
- monitoring a first sampling clock associated with a first analog-to-digital converter;
- monitoring a second sampling clock associated with a second analog-to-digital converter;
- comparing a phase associated with the monitored sampling clocks to provide UP and DOWN control signals;
- integrating the UP and DOWN signals to provide at least one error signal;
- adjusting at least one bias voltage in response to the at least one error signal;
- and
- changing a delay time associated with an adjustable delay circuit in response to the at least one bias voltage, wherein the delay time associated with the adjustable delay circuit is associated with at least one of the first and second sampling clocks.
An apparatus for aligning clock edges associated with sampling in an analog-to-digital converter system that includes first and second analog-to-digital converters, the apparatus comprising:
- a means for monitoring a first sampling clock associated with the first analog-to-digital converter;
- a means for monitoring a second sampling clock associated with the second analog-to-digital converter;
- a means for comparing a phase associated with the monitored sampling clocks to provide UP and DOWN control signals;
- a means for varying at least one error signal in response to the UP and DOWN signals to provide at least one sense signal;
- a means for adjusting at least one control signal in response to the at least one sense signal;
- and
- a means for adjusting at least one of a rising edge and a falling edge associated with an adjustable delay circuit in response to the at least one control signal, wherein the delay time associated with the adjustable delay circuit is associated with at least one of the first and second sampling clocks relative to an input clock signal.
Dependencies are inferred from the claim text.