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US 7,068,113 B2Granted
Burst mode clock and data recovery frequency calibration
AssigneeAgere Systems Inc.
InventorsHrvoje Jasa, Gary D. Polhemus, Kenneth Patrick Snowdon
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AssigneeAgere Systems Inc.
InventorsHrvoje Jasa, Gary D. Polhemus, Kenneth Patrick Snowdon
Estimating the term…
A direct calibration technique significantly tightens a tolerance band between multiple voltage controlled oscillators (VCOs), to correct for slight frequency mismatch between the multiple VCOs. The tightened tolerance band enhances the bit error rate (BER) and/or lengthens the possible consecutive identical digits (CIDs) length, and is particularly useful in integrated circuit applications. A Frequency Locked Loop (FLL), an accumulator, and a DAC are implemented to form a calibration loop that becomes far more digital in nature than a PLL, permitting greater embedded circuit test coverage and ease of integration in VLSI digital technologies. A frequency calibrated loop with digital accumulator and DAC in lieu of a PLL with associated charge pump integrator eliminates the need for large integrated capacitors, sensitivity to drift due to the leakage currents associated with deep sub-micron technologies, and embedded analog voltages which generally cannot be tested.
A method of calibrating a voltage controlled oscillator, comprising:
A method of calibrating a voltage controlled oscillator, comprising:
A method of calibrating a voltage controlled oscillator in a clock and data recovery (CDR) circuit, comprising:
A clock and data recovery circuit, comprising:
An integrated circuit including a clock and data recovery circuit, comprising:
Dependencies are inferred from the claim text.