Phase error cancellation

An integrated circuit comprising:

• a fractional N phase-locked loop circuit including a feedback divider circuit coupled to receive a divide control signal that approximates a divide value over time;
• an integrator coupled to receive an error signal and supply an integrated error signal, the error signal being a difference between the divide value and the divide control signal;
• and
• a first delta sigma modulator coupled to receive the integrated error signal and the error signal and generate a cancellation signal to correct phase errors in the phase-locked loop introduced by the feedback divider circuit.

An apparatus for generating a noise cancellation signal in a fractional-N phase-locked loop, the apparatus comprising:

• means for generating a divide control signal that over time approximates a received divide signal;
• means for generating an error term indicative of a difference between the received divide signal and the generated divide control signal;
• means for receiving the error term and generating an integrated error term therefrom;
• and
• means for generating a phase error cancellation signal by quantizing the integrated error term,
• wherein the means for generating the phase error cancellation signal is coupled to receive the integrated error term.