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US 7,068,090 B2Granted
Amplifier circuit
AssigneeSony Corporation
InventorsAtsushi Hirabayashi, Kenji Komori
Life of this patent
Estimating the term…
Abstract
An amplifier circuit includes a CMOS inverter circuit that eliminates a DC offset caused by variations in characteristics of elements in each manufacturing process and is thus applicable to analog signal processing. The CMOS inverter circuit includes a PMOS transistor, a first NMOS transistor, a second NMOS transistor connected to the first NMOS transistor to increase a source voltage of the first NMOS transistor, and DC offset detecting means for detecting a DC offset and for applying a voltage adjusted so as to reduce the DC offset to a gate of the second NMOS transistor.
Claims7
An amplifier circuit, comprising:
- a first PMOS transistor;
- a first NMOS transistor having a drain connected to a drain of said first PMOS transistor;
- a signal input part connected to a gate of said first PMOS transistor and to a gate of said first NMOS transistor;
- a signal output part connected to said drain of said first PMOS transistor and to said drain of said first NMOS transistor;
- and
- at least one of first voltage shift means and second voltage shift means, said first voltage shift means for increasing a source voltage of said first NMOS transistor to reduce a DC offset, said second voltage shift means for decreasing a source voltage of said first PMOS transistor to reduce the DC offset;
- said first voltage shift means including:
- a second NMOS transistor interposed between a source of said first NMOS transistor and a ground part, and
- a DC offset detecting means for detecting the DC offset and for applying a voltage that is adjustable so as to reduce the DC offset to a gate of said second NMOS transistor;
- said DC offset detecting means including:
- a third PMOS transistor having characteristics that are substantially identical with those of said first PMOS transistor,
- a third NMOS transistor having a drain connected to a drain of said third PMOS transistor and having characteristics that are substantially identical with those of said first NMOS transistor,
- a biasing voltage source for supplying a direct-current bias voltage to a gate of said third PMOS transistor and to a gate of said third NMOS transistor,
- a fourth NMOS transistor having a drain connected to a source of said third NMOS transistor and having characteristics that are substantially identical with those of said second NMOS transistor, and
- an operational amplifier having a non-inverting input part connected to the drain of said third PMOS transistor and to the drain of said third NMOS transistor, an inverting input part connected to the gate of said third PMOS transistor and to the gate of said third NMOS transistor, and an output part connected to the gate of said second NMOS transistor and to a gate of said fourth NMOS transistor.
12 more elements
An amplifier circuit, comprising:
- a first PMOS transistor;
- a first NMOS transistor having a drain connected to a drain of said first PMOS transistor;
- a signal input part connected to a gate of said first PMOS transistor and to a gate of said first NMOS transistor;
- a signal output part connected to said drain of said first PMOS transistor and to said drain of said first NMOS transistor;
- and
- at least one of first voltage shift means and second voltage shift means, said first voltage shift means for increasing a source voltage of said first NMOS transistor to reduce a DC offset, said second voltage shift means for decreasing a source voltage of said first PMOS transistor to reduce the DC offset;
- said second voltage shift means including:
- a second PMOS transistor interposed between a source of said first PMOS transistor and a voltage source;
- and
- a DC offset detecting means for detecting the DC offset and for applying a voltage that is adjustable so as to reduce the DC offset to a gate of said second PMOS transistor;
- said DC offset detecting means including:
- a third PMOS transistor having characteristics that are substantially identical with those of said first PMOS transistor,
- a third NMOS transistor having a drain connected to a drain of said third PMOS transistor and having characteristics that are substantially identical with those of said first NMOS transistor,
- a biasing voltage source for supplying a direct-current bias voltage to a gate of said third PMOS transistor and to a gate of said third NMOS transistor,
- a fourth PMOS transistor having a drain connected to a source of said third PMOS transistor and having characteristics that are substantially identical with those of said second PMOS transistor, and
- an operational amplifier having a non-inverting input part connected to the drain of said third PMOS transistor and to the drain of said third NMOS transistor, an inverting input part connected to the gate of said third PMOS transistor and to the gate of said third NMOS transistor, and an output part connected to the gate of said second PMOS transistor and to a gate of said fourth PMOS transistor.
13 more elements
An amplifier circuit, comprising:
- a first PMOS transistor;
- a first NMOS transistor having a drain connected to a drain of said first PMOS transistor;
- a signal input part connected to a gate of said first PMOS transistor and to a gate of said first NMOS transistor;
- a signal output part connected to the drain of said first PMOS transistor and to the drain of said first NMOS transistor;
- voltage control means for variably controlling a source potential of said first PMOS transistor;
- and
- voltage shift means for increasing a source potential of said first NMOS transistor to eliminate a DC offset, said voltage shift means including:
- a second NMOS transistor interposed between a source of said first NMOS transistor and a ground part, and
- DC offset detecting means for detecting the DC offset and for applying a voltage that is adjustable so as to eliminate the DC offset to a gate of said second NMOS transistor;
- said voltage control means including:
- a second PMOS transistor interposed between a source of said first PMOS transistor and a voltage source, and
- a variable voltage source connected to a gate of said second PMOS transistor;
- said DC offset detecting means including:
- a third PMOS transistor having characteristics that are substantially identical with those of said first PMOS transistor,
- a third NMOS transistor having a drain connected to a drain of said third PMOS transistor and having characteristics that are substantially identical with those of said first NMOS transistor,
- a biasing voltage source for supplying a direct-current bias voltage to a gate of said third PMOS transistor and to a gate of said third NMOS transistor,
- a fourth PMOS transistor interposed between a source of said third PMOS transistor and the variable voltage source and having a gate connected to said variable voltage source and having characteristics that are substantially identical with those of said second PMOS transistor,
- a fourth NMOS transistor interposed between a source of said third NMOS transistor and the ground part, and having characteristics that are substantially identical with those of said second NMOS transistor, and
- an operational amplifier having a non-inverting input part connected to the drain of said third PMOS transistor and to the drain of said third NMOS transistor, an inverting input part connected to the gate of said third PMOS transistor and to the gate of said third NMOS transistor, and an output part connected to the gate of said second NMOS transistor and to a gate of said fourth NMOS transistor.
16 more elements
An amplifier circuit, comprising:
- a first PMOS transistor;
- a first NMOS transistor having a drain connected to a drain of said first PMOS transistor;
- a signal input part connected to a gate of said first PMOS transistor and to a gate of said first NMOS transistor;
- a signal output part connected to the drain of said first PMOS transistor and to the drain of said first NMOS transistor;
- voltage control means for variably controlling a source potential of said first NMOS transistor;
- and
- voltage shift means for decreasing a source potential of said first PMOS transistor to eliminate a DC offset, said voltage shift means including:
- a second PMOS transistor interposed between a source of said first PMOS transistor and a voltage source, and
- DC offset detecting means for detecting the DC offset and applying a voltage that is adjustable so as to eliminate the DC offset to a gate of said second PMOS transistor;
- said voltage control means including:
- a second NMOS transistor interposed between a source of said first NMOS transistor and a ground part;
- and
- a variable voltage source connected to a gate of said second NMOS transistor;
- and
- said DC offset detecting means including:
- a third PMOS transistor having characteristics that are substantially identical with those of said first PMOS transistor;
- a third NMOS transistor having a drain connected to a drain of said third PMOS transistor and having characteristics that are substantially identical with those of said first NMOS transistor;
- a biasing voltage source for supplying a direct-current bias voltage to a gate of said third PMOS transistor and to a gate of said third NMOS transistor;
- a fourth NMOS transistor interposed between a source of said third NMOS transistor and the ground part and having a gate connected to said variable voltage source and having characteristics that are substantially identical with those of said second NMOS transistor;
- a fourth PMOS transistor interposed between a source of said third PMOS transistor and the voltage source and having characteristics that are substantially identical with those of said second PMOS transistor;
- and
- an operational amplifier having a non-inverting input part connected to the drain of said third PMOS transistor and to the drain of said third NMOS transistor, an inverting input part connected to the gate of said third PMOS transistor and to the gate of said third NMOS transistor, and an output part connected to the gate of said second PMOS transistor and to a gate of said fourth PMOS transistor.
19 more elements
Dependencies are inferred from the claim text.