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US 7,068,088 B2Granted
Soft-error rate improvement in a latch
AssigneeHewlett-Packard Development Company, L.P.
InventorJohn T. Petersen
Life of this patent
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Abstract
In a preferred embodiment, the invention provides a circuit and method for reducing soft error events in latches. The input of a first inverter is connected to the output of a second inverter. The input of a second inverter is connected to the output of the first inverter. When the input to the first inverter is disturbed by a soft error event, a signal tristates the first inverter.
Claims2
A tristatable latch for reducing soft errors comprising:
- a) a tristatable inverter, the tristatable inverter having a first input, a second input, a third input, a fourth input, and an output;
- b) a first inverter, the first inverter having an input and an output;
- c) a second inverter, the second inverter having an input and an output;
- d) wherein the first input of the tristatable inverter is connected to the output of the first inverter;
- e) wherein the input of the first inverter is connected to the output of the tristatable inverter;
- f) wherein the input of the second inverter is connected to the input of the first inverter;
- g) wherein the output of the second inverter is connected to the second input of the tristatable inverter;
- h) wherein the third input of the tristatable inverter is connected to a clock signal;
- i) wherein the fourth input of the tristatable inverter is connected to an opposite phase of the clock signal;
- j) wherein the tristatable inverter is tristated when the first input to the tristatable inverter is disturbed by a soft error event;
- k) wherein the tristatable inverter further comprises:
- k.1) a first PFET, the first PFET having a gate, drain and source;
- k.2) a second PFET, the second PFET having a gate, drain and source;
- k.3) a third PFET, the third PFET having a gate, drain, and source;
- k.4) a first NFET, the first NFET having a gate, drain and source;
- k.5) a second NFET, the second NFET having a gate, drain and source;
- k.6) a third NFET, the third NFET having a gate, drain, and source;
- k.7) wherein the source of the first PFET is connected to VDD;
- k.8) wherein the source of the third PFET is connected to VDD;
- k.9) wherein the source of the second NFET is connected to GND;
- k.10) wherein the source of the third NFET is connected to GND;
- k.11) wherein the drain of the first PFET and the drain of the third PFET are connected to the source of the second PFET;
- k.12) wherein the drain of the second PFET and the drain of the first NFET are connected to the output of the tristatable inverter;
- k.13) wherein the source of the first NFET is connected to the drain of the second NFET and the drain of the third NFET;
- k.14) wherein the gate of second PFET and the gate of the first NFET are connected to the first input of the tristatable inverter;
- k.15) wherein the gate of the first PFET and the gate of the second NFET are connected to the second input of the tristatable inverter;
- k.16) wherein the gate of the third NFET is connected to the third input of the tristatable inverter;
- k.17) wherein the gate of the third PFET is connected to the fourth input of the tristatable inverter.
25 more elements
A method for manufacturing a tristatable latch for reducing soft errors comprising:
- a) fabricating a tristatable inverter, the tristatable inverter having a first input, a second input, a third input, a fourth input, and an output;
- b) fabricating a first inverter, the first inverter having an input and an output;
- c) fabricating a second inverter, the second inverter having an input and an output;
- d) wherein the first input of the tristatable inverter is connected to the output of the first inverter;
- e) wherein the input of the first inverter is connected to the output of the tristatable inverter;
- f) wherein the input of the second inverter is connected to the input of the first inverter;
- g) wherein the output of the second inverter is connected to the second input of the tristatable inverter;
- h) wherein the third input of the tristatable inverter is connected to a clock signal;
- i) wherein the fourth input of the tristatable inverter is connected to an opposite phase of the clock signal;
- j) wherein the tristatable inverter is tristated when the first input to the tristatable inverter is disturbed by a soft error event;
- k) wherein the tristatable inverter further comprises:
- k.1) a first PFET, the first PFET having a gate, drain and source;
- k.2) a second PFET, the second PFET having a gate, drain and source;
- k.3) a third PFET, the third PFET having a gate, drain, and source;
- k.4) a first NFET, the first NFET having a gate, drain and source;
- k.5) a second NFET, the second NFET having a gate, drain and source;
- k.6) a third NFET, the third NFET having a gate, drain, and source;
- k.7) wherein the source of the first PFET is connected to VDD;
- k.8) wherein the source of the third PFET is connected to VDD;
- k.9) wherein the source of the second NFET is connected to GND;
- k.10) wherein the source of the third NFET is connected to GND;
- k.11) wherein the drain of the first PFET and the drain of the third PFET are connected to the source of the second PFET;
- k.12) wherein the drain of the second PFET and the drain of the first NFET are connected to the output of the tristatable inverter;
- k.13) wherein the source of the first NFET is connected to the drain of the second NFET and the drain of the third NFET;
- k.14) wherein the gate of second PFET and the gate of the first NFET are connected to the first input of the tristatable inverter;
- k.15) wherein the gate of the first PFET and the gate of the second NFET are connected to the second input of the tristatable inverter;
- k.16) wherein the gate of the third NFET is connected to the third input of the tristatable inverter;
- k.17) wherein the gate of the third PFET is connected to the fourth input of the tristatable inverter.
25 more elements
Dependencies are inferred from the claim text.