Method and apparatus for an improved timer circuit and pulse width detection

A timer circuit, comprising:

• a ramp timer responsive to an input signal for generating a ramp signal and providing an end of ramp signal at an output when said ramp signal attains a predetermined amplitude;
• a counter responsive to a clock signal for counting a predetermined number of clock cycles, said input signal causing an enabling of said counter to count said cycles of said clock signal;
• a timer control circuit for pausing said ramp signal of said ramp timer upon an occurrence of a first clock cycle following said enabling of said counter, and for restarting said ramp signal upon an occurrence of a last one of said predetermined number of clock cycles counted by said counter;
• and
• a timer latch circuit for providing an output timing signal, wherein said output timing signal of said timer latch is set by said input signal and reset by said end of ramp signal.

A timer circuit comprising:

• means for generating a ramp timing signal, said ramp timing signal being initiated upon an occurrence of an input signal;
• means for counting a predetermined number of clock cycles, said occurrence of said input signal causing an enabling of said means for counting;
• means for pausing said ramp timing signal upon the occurrence of a first clock cycle following said enabling of said means for counting, and for restarting said ramp timing signal upon an occurrence of a last one of said predetermined number of clock cycles counted by said means for counting;
• means for generating a signal denoting an end of ramp timing signal;
• and
• means for receiving said input signal and said end of ramp timing signal and providing an output timing signal in response thereto.

A glitch trigger circuit, comprising:

• a timer circuit, comprising;
• a ramp timer responsive to an input signal for generating a ramp signal and providing an end of ramp signal at an output;
• a counter responsive to a clock signal for counting a predetermined number of clock cycles, said input signal causing an enabling of said counter;
• a timer control circuit for pausing said ramp signal of said ramp timer upon the occurrence of a first clock cycle following said enabling of said counter, and for restarting said ramp signal from a level attained when said ramp signal was paused upon an occurrence of a last one of said predetermined number of clock cycles counted by said counter;
• and
• a timer latch circuit for providing an output timing signal having a predetermined duration;
• and
• a D flip-flop circuit responsive to said output timing signal for providing a trigger output signal if said input signal exhibits a pulse width less than said duration of said output timing signal.

A glitch trigger filter, comprising:

• a timer circuit, comprising:
• a ramp timer for generating a ramp signal and providing an end of ramp signal at an output;
• a counter responsive to a clock signal for counting a predetermined number of clock cycles, said input signal causing an enabling of said counter;
• a timer control circuit for pausing said ramp signal of said ramp timer upon the occurrence of a first clock cycle following said enabling of said counter, and for restarting the ramp signal upon an occurrence of a last one of said predetermined number of clock cycles counted by said counter;
• and
• a timer latch for providing an output timing signal;
• and
• a D flip-flop circuit responsive to said output timing signal for providing a trigger output signal if said input signal exhibits a pulse width greater than said duration of said output timing signal.

A trigger hold-off timer circuit, comprising:

• a timer circuit, comprising:
• a ramp timer for generating a ramp signal and for providing an end of ramp signal at an output;
• a counter responsive to a clock signal for counting a predetermined number of clock cycles, said input signal causing an enabling of said counter;
• a timer control circuit for pausing the ramp signal of said ramp timer upon the occurrence of a first clock cycle following said enabling of said counter, and for restarting said ramp signal upon an occurrence of a last one of said predetermined number of clock cycles counted by said counter;
• and
• a timer latch circuit for providing a hold-off output signal to a first flip-flop circuit for maintaining a logic level of said first flip-flop for a predetermined time interval;
• said first flip-flop circuit asserting an Accepted Trigger signal;
• and
• a second flip-flop circuit for producing an output signal in response to said Accepted Trigger signal to provide a control input to said timer circuit.

A timer circuit, comprising:

• a ramp timer responsive to an input signal for generating a ramp signal and providing an end of ramp signal;
• a counter responsive to a clock signal for counting a predetermined number of clock cycles, said input signal causing an enabling of said counter;
• a timer control circuit for pausing the ramp signal of said continuous timer at a level upon the occurrence of a first clock cycle following said enabling of said counter, and for restarting the ramp signal from said level upon an occurrence of a last one of said predetermined number of clock cycles counted by said counter;
• and
• a logic gate for combining said input signal and said end of ramp signal for providing an output timing signal.