Phase correction circuit

Abstract

There is provided a phase correction circuit capable of detecting a skew between a data signal and a clock signal without requiring a clock signal as pattern data upon initialization. The phase correction circuit is configured to include a variable delay device 10 to which a data signal in a DDR format is inputted, a first F/F 1 which fetches a delayed data signal in synchronization with the clock signal, a second F/F 2 which fetches the delayed data signal in synchronization with a reverse clock signal, a third F/F 3 which fetches an output signal from the first F/F 1 in synchronization with the clock signal, and a fourth F/F 4 which fetches an output signal from the second F/F 2 in synchronization with the clock signal, and the phase correction circuit further includes a fifth F/F 5 which fetches a rate signal having the same cycle as that of the data signal in synchronization with the clock signal, a sixth F/F 6 which fetches an output signal from the fifth F/F 5 in synchronization with the clock signal, and an AND circuit 8 to which an output signal from the third F/F 3 and an output signal from the sixth F/F 6 are inputted.

Dependencies are inferred from the claim text.