Delay locked loop capable of compensating for delay of internal clock signal by variation of driving strength of output driver in semiconductor memory device

A delay locked loop (DLL) of a semiconductor memory device comprising:

• a replica output driver which has a replica delay amount that is the same as an output delay amount of an output driver coupled thereto, the driving strength of which varies;
• a phase detector which detects a phase difference between an internal clock signal which is delayed through the replica output driver by the replica delay amount, and an external clock signal;
• a control circuit which generates a control signal in response to an output signal of the phase detector;
• and
• a variable delay circuit which, in response to the control signal, delays the external clock signal and generates the internal clock signal in synchronization with the external clock signal, wherein the driving strength of the output driver varies in response to a driver impedance control signal generated by the semiconductor memory device, and in response to the driver impedance control signal, the replica output driver has the same delay amount as the delay amount of the internal clock signal generated by the output driver.