Frequency synthesizer with digital phase selection

A method, comprising:

• receiving a first clock signal;
• generating a set of N second signals from the first clock signal by processing the first clock signal into divided down signals having mutually exclusive phases, N being an integer;
• selecting one of the N second signals to provide as an output clock signal;
• and
• digitally controlling a clock output signal logic to change within a time period not greater than one cycle of the first clock signal, from providing a first output clock signal derived from a member of the set of N second signals to providing a second output clock signal derived from the set of N second signals, where changing from the first output clock signal to the second output clock signal changes the frequency of the provided output clock signal, where the phase of the provided output clock signal is determined by:
• Phase(t+1)=Phase(t)+M
• where t is a phase number of the current provided output clock signal, Phase (t) is a signal phase of the current provided output clock signal, Phase (t+1) is a signal phase of the next provided output clock signal, and M is a frequency divisor, M being an integer in the range 0 to (N−1).

A method for responding to a supply voltage change within one clock cycle of a reference clock whose frequency is related to the supply voltage, comprising:

• receiving a reference clock signal with a frequency Fmax from the reference clock;
• generating N different signals from the reference clock signal using a phase multiplexing technique, where each of the N different signals is phase shifted by (n/N) of a cycle from the phase of the reference clock signal, where N and n are integers, n being in the range 0 to (N−1);
• receiving a first control signal configured to establish an initial frequency divisor m that facilitates providing a first output clock signal with a first frequency;
• providing the first output clock signal where the first frequency is characterized by Fout=Fmax*(N/(N+m)), m being an integer in the range 0 to (N−1);
• tracking the frequency divisor m;
• tracking a phase of the output clock signal;
• receiving a second control signal configured to establish a second frequency divisor m′ that facilitates providing a second output clock signal with a second frequency of Fout=Fmax*(N/N+m′)) and where the second frequency divisor facilitates producing the second output clock signal by shifting to a second input signal from the N different signals, where the second input signal has a phase shift determined according to Ph(t+1)=Phase(t)+m′;
• and
• digitally controlling an output clock signal provider to switch to providing the second output clock signal in a single cycle of the reference clock signal.

A computer-readable medium storing processor executable instructions operable to perform a method for responding to a supply voltage change within one clock cycle of a clock whose frequency is related to the supply voltage, the method comprising:

• receiving a reference clock signal with a frequency Fmax from the reference clock;
• generating N different signals from the reference clock signal using a phase multiplexing technique, where each of the N different signals is phase shifted by (n/N) of a cycle from the phase of the reference clock signal, where N and n are integers, n being in the range 0 to (N−1);
• receiving a first control signal configured to establish an initial frequency divisor m that facilitates providing a first output clock signal with a first frequency;
• providing the first output clock signal where the first frequency is characterized by Fout=Fmax*(N/(N+m)), m being an integer in the range 0 to (N−1);
• tracking the frequency divisor m;
• tracking a phase of the output clock signal;
• receiving a second control signal configured to establish a second frequency divisor m′ that facilitates providing a second output clock signal with a second frequency of Fout=Fmax*(N/N+m′)) and where the second frequency divisor facilitates producing the second output clock signal by shifting to a second input signal from the N different signals, where the second input signal has a phase shift determined according to Ph(t+1)=Phase(t)+m′;
• and
• digitally controlling an output clock signal provider to switch to providing the second output clock signal in a single cycle of the reference clock signal.