Customizable and programmable cell array

A semiconductor device comprising:

• a logic array comprising a multiplicity of logic cells, said logic cells having a multiplicity of inputs and a multiplicity of outputs, each logic cell including at least one flip-flop and at least one multiplexer, said logic array also comprising at least one standard metal layer;
• and
• metal connection layers overlying said logic array for interconnecting various inputs and outputs thereof in a customized manner;
• wherein the connections between at least one of said multiplexers and one of said flip-flops are customized to create at least one flip-flop with synchronous preset.

A customizable logic array comprising:

• an array of logic cell having a multiplicity of inputs and a multiplicity of outputs;
• and
• customized interconnections permanently interconnecting at least a plurality of said multiplicity of inputs and at least a plurality of said multiplicity of outputs, wherein each of at least some of said logic cells comprises at least one flip-flop;
• and
• a clock tree providing clock inputs to some of said flip-flops, wherein said clock tree comprises:
• a clock input;
• a clock signal;
• an inverted clock signal;
• and
• a power saving circuit.

A semiconductor device comprising:

• a plurality of logic cells having a multiplicity of inputs and a multiplicity of outputs, wherein each of at least some of said logic cells comprises at least one flip-flop;
• and
• a clock tree providing clock inputs to some of said flip-flops, wherein said clock tree comprises:
• a clock input;
• a clock signal;
• an inverted clock signal;
• a power saving circuit;
• and
• control logic,
• wherein said control logic provides a pulse to said power saving circuit on each transition of said clock input to short said clock signal and said inverted clock signal together.

A customizable logic array comprising:

• an array of logic cells, having a multiplicity of inputs, a multiplicity of outputs, and at least one look up table with address decode;
• a multiplicity of X decoders, each connected to a multiplicity of said look up table, with a multiplicity of word lines;
• a multiplicity of Y decoders, each connected to a multiplicity of said look up table, with a multiplicity of bit lines;
• and
• customized interconnections permanently interconnecting at least a plurality of said multiplicity of inputs and at least a plurality of said multiplicity of outputs, wherein
• in a first state, said X decoders, said Y decoders, said word lines, said bit lines and said look up tables, function as a dual port memory;
• and
• in a second state said Y decoders, said word lines and said bit lines function to program said look up tables.

A semiconductor device comprising:

• an array of logic array including a multiplicity of logic cells, and metal connection layers overlying the multiplicity of logic cells for providing at least one permanent customized direct interconnect between various inputs and outputs thereof,
• wherein each logic cell comprises:
• at least one look-up table;
• and
• at least one tristate inverter.