Control circuit and reconfigurable logic block

A reconfigurable logic block, comprising:

• an input circuit configured to acquire reconfiguration data of logic gates for building a plurality of logic circuits;
• a memory array having a plurality of memory units corresponding to a number of the plurality of logic circuits, the memory units including paired first and second variable resistive memories, configured to store the reconfiguration data based on a magnitude relation of resistance between the first and second variable resistive memories in accordance with a write signal corresponding to the reconfiguration data;
• an inverted logic gate array having a plurality of inverted logic gate units corresponding to the memory units, each of the inverted logic gate units having a latch circuit, which includes a first inverted logic gate and a second inverted logic gate, the inverted logic gate unit connected respectively to the first variable resistive memory between an output of the first inverted logic gate and an input of the second inverted logic gate, and the second variable resistive memory between an input of the first inverted logic gate and an output of the second inverted logic gate, the inverted logic gate units configured to transmit the configuration signal by reading out the reconfiguration data from the memory units;
• a selection circuit configured to transmit a selection signal for the reconfiguration data to the inverted logic gate array;
• and
• a reconfigurable logic gate configured to rebuild the logic gates in accordance with the configuration signal corresponding to the reconfiguration data selected by the selection signal.