Memory module with dynamic termination using bus switches timed by memory clock and chip select

A memory module with low-power termination comprising:

• a printed-circuit board (PCB) substrate having wiring traces formed thereon;
• a clock line on the substrate for carrying a clock signal;
• a chip-select line on the substrate for carrying a chip-select signal;
• a plurality of synchronous memory chips, each having a clock input receiving the clock signal from the clock line and a chip-select input receiving the chip-select signal from the chip-select line and each receiving a plurality of signal inputs;
• a plurality of signal lines on the substrate to the signal inputs of the plurality of synchronous memory chips, each signal line having a driven end and one or more far end;
• a plurality of active terminators, each connected between a far end of one of the plurality of signal lines and a terminating voltage, the plurality of active terminators each receiving a switch signal;
• wherein each active terminator in the plurality of active terminators comprises:
• a static terminating resistor connected between the far end and the terminating voltage and having a resistance of 1K ohm or more;
• a dynamic terminating resistor and a switch connected together in series between the far end and the terminating voltage;
• wherein the dynamic terminating resistor has a resistance of less than 100 ohms and selected to approximately match an impedance of a signal line connected to the far end;
• wherein the switch comprises an n-channel transistor with a gate receiving the switch signal or an inverse of the switch signal, wherein the n-channel transistor conducts current through the dynamic terminating resistor when the switch signal is activated, but prevents current flow through the dynamic terminating resistor when the switch signal is not activated;
• and
• switch timing logic, receiving the chip-select signal and the clock signal, for pulsing activate the switch signal when the chip-select signal selects the plurality of synchronous memory chips for access during a portion of a period of the clock signal.

An actively-terminated memory module comprising:

• substrate means, with metal contact pads along an edge of the substrate means, for insertion into a socket on a main board;
• a plurality of memory chips mounted on the substrate means;
• terminated signal line means, on the substrate means and connected to inputs on the plurality of memory chips, for conducting a signal from a driven end to a far end, the driven end being driven by a driver on the substrate means or on the main board, and the far end being farther along the terminated signal line means than is the driven end;
• high-current resistor means for terminating the terminated signal line means with a low impedance;
• switch means for selectively connecting the high-current resistor means to the far end in response to a switch signal being in an active state, but for disconnecting the high-current resistor means from the far end in response to the switch signal being in an inactive state;
• a clock signal and a chip-select signal carried by lines on the substrate means, wherein the chip-select signal is activated when the main board accesses the plurality of memory chips and wherein the plurality of memory chips operate synchronously to the clock signal when the chip-select signal is activated;
• and
• switch-signal generator means, mounted on the substrate means, receiving the chip-select signal and the clock signal, the switch-signal generator means generating the switch signal in the active state synchronously to the clock signal when the chip-select signal is activated to select the plurality of memory chips for access by the main board,
• whereby the high-current resistor means terminates the terminated signal line means in response to the switch signal.