US 7,068,063 B2Granted

Output buffer circuit

AssigneeOki Electric Industry Co., Ltd.

InventorToshimichi Seike

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Abstract

An output buffer circuit includes first and second inverters connected to an input terminal for outputting signals having a slow rise up and fall down characteristic; a pull up control circuit that pulls up an output voltage of the first inverter and stops the pull up operation based on a level of the output signal of the first inverter; and a pull down control circuit that pulls down an output voltage of the second inverter and stops the pull down operation based on a level of the output signal of the second inverter. A first output transistor has a source connected to a first power source, a drain connected to the output terminal and a gate connected to the first inverter. A second output transistor has a source connected to a second power source, a drain connected to the output terminal and a gate connected to the second inverter.

Claims8

Dependent claims

An output buffer circuit comprising:

an input terminal for receiving an input signal;
an output terminal for outputting an output signal;
a first inverter connected to the input terminal, the first inverter outputting a first signal having a slow rise up and fall down characteristic;
a second inverter connected to the input terminal, the second inverter outputting a second signal having the slow rise up and fall down characteristic;
a pull up control circuit connected to the input terminal, the pull up control circuit including a delay circuit that is connected to the input terminal and that has third inverters connected in series that provide a delayed input signal,
the pull up control circuit pulling up a voltage of the first signal under control of the delayed input signal during a predetermined time from a time when the input signal is changed from “L” level to “H” level;
a pull down control circuit connected to the input terminal, the pull down control circuit pulling down a voltage of the second signal during a predetermined time from a time when the input signal is changed from “H” level to “L” level;
a first output transistor having a source connected to a first power source potential node, a drain connected to the output terminal and a gate connected to the first inverter so as to receive the first signal;
and
a second output transistor having a source connected to a second power source potential node, a drain connected to the output terminal and a gate connected to the second inverter so as to receive the second signal.

7 more elements

An output buffer circuit comprising:

an input terminal for receiving an input signal;
an output terminal for outputting an output signal;
a first inverter connected to the input terminal, the first inverter outputting a first signal having a slow rise up and fall down characteristic;
a second inverter connected to the input terminal, the second inverter outputting a second signal having the slow rise up and fall down characteristic;
a pull up control circuit connected to the input terminal, the pull up control circuit pulling up a voltage of the first signal during a predetermined time from a time when the input signal is changed from “L” level to “H” level;
a pull down control circuit connected to the input terminal, the pull down control circuit pulling down a voltage of the second signal during a predetermined time from a time when the input signal is changed from “H” level to “L” level;
a first output transistor having a source connected to a first power source potential node, a drain connected to the output terminal and a gate connected to the first inverter so as to receive the first signal;
and
a second output transistor having a source connected to a second power source potential node, a drain connected to the output terminal and a gate connected to the second inverter so as to receive the second signal,
wherein each of the first and second inverters comprises
an inverter input terminal,
an inverter output terminal,
a first inverter transistor of a first conductivity type having a back gate connected to the second power source potential node, a first terminal, and a second terminal and a gate connected together with the first power source potential node,
a second inverter transistor of a second conductivity type having a back gate connected to the first power source potential node, a first terminal connected to the first terminal of the first inverter transistor, a second terminal connected to the inverter output terminal and a gate connected to the inverter input terminal,
a third inverter transistor of the second conductivity type having a back gate connected to the first power source potential node, a first terminal, and a second terminal and a gate connected together with the second power source potential node, and
a fourth inverter transistor of the first conductivity type having a back gate connected to the second power source potential node, a first terminal connected to the first terminal of the third inverter transistor, a second terminal connected to the inverter output terminal and a gate connected to the inverter input terminal.

13 more elements

An output buffer circuit comprising:

an input terminal for receiving an input signal;
an output terminal for outputting an output signal;
a first inverter connected to the input terminal, the first inverter outputting a first signal having a slow rise up and fall down characteristic;
a second inverter connected to the input terminal, the second inverter outputting a second signal having the slow rise up and fall down characteristic;
a pull up control circuit connected to the input terminal, the pull up control circuit pulling up a voltage of the first signal during a predetermined time from a time when the input signal is changed from “L” level to “H” level;
a pull down control circuit connected to the input terminal, the pull down control circuit pulling down a voltage of the second signal during a predetermined time from a time when the input signal is changed from “H” level to “L” level;
a first output transistor having a source connected to a first power source potential node, a drain connected to the output terminal and a gate connected to the first inverter so as to receive the first signal;
and
a second output transistor having a source connected to a second power source potential node, a drain connected to the output terminal and a gate connected to the second inverter so as to receive the second signal,
wherein each of the first and second inverters comprises
an inverter input terminal,
an inverter output terminal,
a first inverter transistor of a first conductivity type having a back gate connected to the first power source potential node, a first terminal, a second terminal connected to the inverter output terminal and a gate connected to the inverter input terminal,
a first diode connected between the first power source potential node and the first terminal of the first inverter transistor for pulling down a voltage supplied from the first power source potential node,
a second inverter transistor of a second conductivity type having a back gate connected to the second power source potential node, a first terminal, a second terminal connected to the inverter output terminal and a gate connected to the inverter input terminal, and
a second diode connected between the second power source potential node and the first terminal of the second inverter transistor for pulling down a voltage supplied from the first terminal of the second inverter transistor.

13 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/752,010Filed 7 Jan 2004 · division
Priority: JP 2001-21537616 Jul 2001
Published: US 2004/0135597 A115 Jul 2004
Granted: 27 Jun 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H03K 17/166
By feedback from the output circuit to the control circuit: soft switching
H03K 19/0013
Arrangements for reducing power consumption: in field effect transistor circuits
H03K 19/09429
Multistate logic: one of the states being the high impedance or floating state
H03K 2217/0018
Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00: special modifications or…

Family

Application10/194,297Parent of this division · filed 15 Jul 2002
US 2004/0135597 A1Pre-grant publication · published 15 Jul 2004
US 6,720,794 B2Parent of this division
US 2003/0011402 A1Published application
US 7,068,063 B2This patent

From the US filing history. Foreign family members aren’t listed.