Residual current detection circuit
AssigneeShakira Limited
InventorPatrick Ward
Life of this patent
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Abstract
A residual current detection circuit comprises a current transformer CT for detecting an imbalance current indicative of a residual current and a full wave restifier FWR for providing an output whose amplitude corresponds to the magnitude of the residual current. The FWR output is applied simultaneously to two channels. The first channel includes a first comparator COMP1 to provide a first signal which persists during periods when the amplitude of the output exceeds a first level. The second channel includes a capacitor C2 which acquires a charge corresponding to the output level and a second comparator COMP2 for providing a second signal in response to the capacitor voltage exceeding a second level. An output is provided from the circuit only when the first signal is coincident with the second signal.
Claims9
A residual current detection circuit comprising means for detecting an imbalance current indicative of a residual current and providing an output whose amplitude corresponds to the magnitude of the residual current, the output being applied simultaneously to two channels wherein the first channel provides a first signal while the amplitude of the output exceeds a predetermined level and the second channel provides a second signal, the first and second signals being applied to a circuit stage which produces an output only when the applied first and second signals are coincident, wherein the application of the second signal to the circuit stage is delayed with respect to the application of the first signal to the circuit stage whereby the circuit stage produces an output only if the duration of the first signal is greater than the delay in the application of the second signal.
A residual current detection circuit comprising means for detecting an imbalance current indicative of a residual current and providing an output whose amplitude corresponds to the magnitude of the residual current, the output being applied simultaneously to two channels wherein the first channel includes means for providing a first signal while the amplitude of the output exceeds a first level, and wherein the second channel includes a capacitor which acquires a charge corresponding to the amplitude of the output and means for providing a second signal in response to the voltage on the capacitor exceeding a second level, the circuit further including a circuit stage for providing an output signal only when the applied first and second signals are coincident, wherein the application of the second signal to the circuit stage is delayed with respect to the application of the first signal to the circuit stage whereby the output signal is provided by the circuit stage only if the duration of the first signal is greater than the delay in the application of the second signal.
Dependencies are inferred from the claim text.