Back to results
US 7,067,927 B1Granted
Die with integral pedestal having insulated walls
AssigneeNational Semiconductor Corporation
InventorShahram Mostafazadeh
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeNational Semiconductor Corporation
InventorShahram Mostafazadeh
Estimating the term…
A variety of techniques and structures are described that integrate an insulated pedestal into the back surface of integrated circuit dice. The die has an insulated integral pedestal formed therein that acts as a spacer. The pedestal has a footprint that is smaller than the total footprint of the die so that a portion of the active region of the die overhangs the pedestal. The geometry of the pedestal may be widely varied and in some embodiments, multiple pedestals may be provided on the stacked die. In another aspect, the pedestals are formed at the wafer level such that the pedestals are defined in the back surface of the wafer. Often, the thickness of the pedestals will be thicker than the portions of the wafer outside the pedestal areas. The described dice are particularly well suited for use in stacked die packages.
An integrated circuit package comprising:
A semiconductor device comprising a die having an active surface, a bottom surface, an active region, a pedestal on the bottom surface and an electrical insulating layer, the pedestal being integrally formed with the active region and including sidewalls, and the electrical insulating layer being arranged to cover at least portions of the sidewalls of the pedestal, wherein the insulating layer only coats and covers portions of the die and does not encapsulate any other structures, whereby the insulated pedestal has a smaller footprint than a total footprint of the die so that portions of the bottom surface of the die are recessed relative to a bottom surface of the pedestal.
An integrated circuit wafer comprising a multiplicity of dice as:
Dependencies are inferred from the claim text.