Three-dimensional stacked semiconductor package with metal pillar in encapsulant aperture

A three-dimensional stacked semiconductor package, comprising:

• a first semiconductor chip assembly, comprising:
• a first semiconductor chip that includes first and first opposing surfaces, wherein the first surface of the first chip includes a first conductive pad;
• a first conductive trace that includes a first routing line, a first metal particle and a first metal pillar;
• a first connection joint that electrically connects the first routing line and the first pad;
• and
• a first encapsulant that includes first and second opposing surfaces, wherein the first surface of the first encapsulant faces in a first direction, the second surface of the first encapsulant faces in a second direction opposite the first direction, the first chip and the first metal particle are embedded in the first encapsulant, the first chip, the first metal particle and the first encapsulant extend vertically beyond the first routing line in the first direction, the first routing line extends laterally beyond the first metal particle and the first metal pillar towards the first chip and extends vertically beyond the first chip and the first metal particle in the second direction, the first metal particle overlaps and is non-integral with the first routing line and the first metal pillar, is disposed outside a periphery of the first chip and extends vertically across at least some of a thickness of the first chip between the first and second surfaces of the first chip, the first metal pillar is devoid of solder and conductive adhesive, contacts and is non-integral with the first routing line, is disposed outside the periphery of the first chip and extends vertically beyond the first chip, the first routing line, the first metal particle and the first encapsulant in the second direction, and any chip embedded in the first encapsulant is electrically connected to the first metal particle by an electrically conductive path that includes the first routing line;
• and
• a second semiconductor chip assembly, comprising:
• a second semiconductor chip that includes first and second opposing surfaces, wherein the first surface of the second chip includes a second conductive pad;
• a second conductive trace that includes a second routing line and a second metal particle;
• a second connection joint that electrically connects the second routing line and the second pad;
• and
• a second encapsulant that includes first and second opposing surfaces, wherein the first surface of the second encapsulant faces in the first direction, the second surface of the second encapsulant faces in the second direction, a second aperture in the second encapsulant extends from the first surface of the second encapsulant to the second metal particle, extends into but not through the second encapsulant, is spaced from the second routing line and is disposed outside a periphery of the second chip, the second chip and the second metal particle are embedded in the second encapsulant, the second chip, the second metal particle and the second encapsulant extend vertically beyond the second routing line in the first direction, the second routing line extends laterally beyond the second metal particle towards the second chip and extends vertically beyond the second chip and the second metal particle in the second direction, the second metal particle overlaps and is non-integral with the second routing line, is disposed outside the periphery of the second chip and extends vertically across at least some of a thickness of the second chip between the first and second surfaces of the second chip, and any chip embedded in the second encapsulant is electrically connected to the second metal particle by an electrically conductive path that includes the second routing line;
• wherein the first assembly overlaps the second assembly, the first surface of the second encapsulant faces towards the second surface of the first encapsulant, the first metal pillar extends into the second aperture, is disposed vertically beyond the second routing line in the first direction and is electrically connected to the second metal particle within the second encapsulant, the first and second routing lines are spaced from and vertically aligned with one another, and the first and second metal particles are spaced from and vertically aligned with one another.

A three-dimensional stacked semiconductor package, comprising:

• a first semiconductor chip assembly, comprising:
• a first semiconductor chip that includes first and first opposing surfaces, wherein the first surface of the first chip includes a first conductive pad;
• a first conductive trace that includes a first routing line, a first metal particle and a first metal pillar;
• a first connection joint that electrically connects the first routing line and the first pad;
• and
• a first encapsulant that includes first and second opposing surfaces, wherein the first surface of the first encapsulant faces in a first direction, the second surface of the first encapsulant faces in a second direction opposite the first direction, a first aperture in the first encapsulant extends from the first surface of the first encapsulant to the first metal particle, extends into but not through the first encapsulant, is spaced from the first routing line and the first metal pillar and is disposed outside a periphery of the first chip, the first chip and the first metal particle are embedded in the first encapsulant, the first chip, the first metal particle and the first encapsulant extend vertically beyond the first routing line in the first direction, the first routing line extends laterally beyond the first metal particle and the first metal pillar towards the first chip and extends vertically beyond the first chip and the first metal particle in the second direction, the first metal particle overlaps and is non-integral with the first routing line and the first metal pillar, is disposed outside the periphery of the first chip and extends vertically across at least some of a thickness of the first chip between the first and second surfaces of the first chip, the first metal pillar is devoid of solder and conductive adhesive, contacts and is non-integral with the first routing line, is disposed outside the periphery of the first chip and extends vertically beyond the first chip, the first routing line, the first metal particle and the first encapsulant in the second direction, the first conductive trace includes solder or conductive adhesive that contacts and overlaps the first routing line and overlaps the first metal pillar, and any chip embedded in the first encapsulant is electrically connected to the first metal particle by an electrically conductive path that includes the first routing line;
• and
• a second semiconductor chip assembly, comprising:
• a second semiconductor chip that includes first and second opposing surfaces, wherein the first surface of the second chip includes a second conductive pad;
• a second conductive trace that includes a second routing line, a second metal particle and a second metal pillar;
• a second connection joint that electrically connects the second routing line and the second pad;
• and
• a second encapsulant that includes first and second opposing surfaces, wherein the first surface of the second encapsulant faces in the first direction, the second surface of the second encapsulant faces in the second direction, a second aperture in the second encapsulant extends from the first surface of the second encapsulant to the second metal particle, extends into but not through the second encapsulant, is spaced from the second routing line and the second metal pillar and is disposed outside a periphery of the second chip, the second chip and the second metal particle are embedded in the second encapsulant, the second chip, the second metal particle and the second encapsulant extend vertically beyond the second routing line in the first direction, the second routing line extends laterally beyond the second metal particle and the second metal pillar towards the second chip and extends vertically beyond the second chip and the second metal particle in the second direction, the second metal particle overlaps and is non-integral with the second routing line and the second metal pillar, is disposed outside the periphery of the second chip and extends vertically across at least some of a thickness of the second chip between the first and second surfaces of the second chip, the second metal pillar is devoid of solder and conductive adhesive, contacts and is non-integral with the second routing line, is disposed outside the periphery of the second chip and extends vertically beyond the second chip, the second routing line, the second metal particle and the second encapsulant in the second direction, the second conductive trace includes solder or conductive adhesive that contacts and overlaps the second routing line and overlaps the second metal pillar, and any chip embedded in the second encapsulant is electrically connected to the second metal particle by an electrically conductive path that includes the second routing line;
• wherein the first assembly overlaps the second assembly, the first surface of the second encapsulant faces towards the second surface of the first encapsulant, the first metal pillar extends into the second aperture, is disposed vertically beyond the second routing line in the first direction and is electrically connected to the second metal particle within the second encapsulant, the first and second routing lines are spaced from and vertically aligned with one another, the first and second metal particles are spaced from and vertically aligned with one another, and the first and second metal pillars are spaced from and vertically aligned with one another.

A three-dimensional stacked semiconductor package, comprising:

• a first semiconductor chip assembly, comprising:
• a first semiconductor chip that includes first and first opposing surfaces, wherein the first surface of the first chip includes a first conductive pad;
• a first conductive trace that includes a first routing line, a first metal particle and a first metal pillar;
• a first connection joint that electrically connects the first routing line and the first pad;
• and
• a first encapsulant that includes first and second opposing surfaces, wherein the first surface of the first encapsulant faces in a first direction, the second surface of the first encapsulant faces in a second direction opposite the first direction, a first aperture in the first encapsulant extends from the first surface of the first encapsulant to the first metal particle, extends into but not through the first encapsulant, is spaced from the first routing line and the first metal pillar and is disposed outside a periphery of the first chip, the first chip and the first metal particle are embedded in the first encapsulant, the first chip, the first metal particle and the first encapsulant extend vertically beyond the first routing line in the first direction, the first routing line extends laterally beyond the first metal particle and the first metal pillar towards the first chip and extends vertically beyond the first chip and the first metal particle in the second direction, the first metal particle is solder, contacts and overlaps and is non-integral with the first routing line, overlaps and is non-integral with the first metal pillar, is disposed outside the periphery of the first chip and extends vertically across at least some of a thickness of the first chip between the first and second surfaces of the first chip, the first metal pillar is devoid of solder and conductive adhesive, contacts and is non-integral with the first routing line, is disposed outside the periphery of the first chip and extends vertically beyond the first chip, the first routing line, the first metal particle and the first encapsulant in the second direction, and any chip embedded in the first encapsulant is electrically connected to the first metal particle by an electrically conductive path that includes the first routing line;
• and
• a second semiconductor chip assembly, comprising:
• a second semiconductor chip that includes first and second opposing surfaces, wherein the first surface of the second chip includes a second conductive pad;
• a second conductive trace that includes a second routing line, a second metal particle and a second metal pillar;
• a second connection joint that electrically connects the second routing line and the second pad;
• and
• a second encapsulant that includes first and second opposing surfaces, wherein the first surface of the second encapsulant faces in the first direction, the second surface of the second encapsulant faces in the second direction, a second aperture in the second encapsulant extends from the first surface of the second encapsulant to the second metal particle, extends into but not through the second encapsulant, is spaced from the second routing line and the second metal pillar and is disposed outside a periphery of the second chip, the second chip and the second metal particle are embedded in the second encapsulant, the second chip, the second metal particle and the second encapsulant extend vertically beyond the second routing line in the first direction, the second routing line extends laterally beyond the second metal particle and the second metal pillar towards the second chip and extends vertically beyond the second chip and the second metal particle in the second direction, the second metal particle is solder, contacts and overlaps and is non-integral with the second routing line, overlaps and is non-integral with the second metal pillar, is disposed outside the periphery of the second chip and extends vertically across at least some of a thickness of the second chip between the first and second surfaces of the second chip, the second metal pillar is devoid of solder and conductive adhesive, contacts and is non-integral with the second routing line, is disposed outside the periphery of the second chip and extends vertically beyond the second chip, the second routing line, the second metal particle and the second encapsulant in the second direction, and any chip embedded in the second encapsulant is electrically connected to the second metal particle by an electrically conductive path that includes the second routing line;
• wherein the first assembly overlaps the second assembly, the first surface of the second encapsulant faces towards the second surface of the first encapsulant, the first metal pillar extends into the second aperture, extends into and contacts and is embedded in and is electrically connected to in the second metal particle within the second encapsulant and is disposed vertically beyond the second routing line in the first direction, the first and second routing lines are spaced from and vertically aligned with one another, the first and second metal particles are spaced from and vertically aligned with one another, and the first and second metal pillars are spaced from and vertically aligned with one another.

A three-dimensional stacked semiconductor package, comprising:

• a first semiconductor chip assembly, comprising:
• a first semiconductor chip that includes first and first opposing surfaces, wherein the first surface of the first chip includes a first conductive pad;
• a first conductive trace that includes a first routing line, a first metal particle, a first conductive bond and a first metal pillar;
• a first connection joint that electrically connects the first routing line and the first pad;
• and
• a first encapsulant that includes first and second opposing surfaces, wherein the first surface of the first encapsulant faces in a first direction, the second surface of the first encapsulant faces in a second direction opposite the first direction, a first aperture in the first encapsulant extends from the first surface of the first encapsulant to the first metal particle, extends into but not through the first encapsulant, is spaced from the first routing line and the first metal pillar and is disposed outside a periphery of the first chip, the first chip and the first metal particle are embedded in the first encapsulant, the first chip, the first metal particle and the first encapsulant extend vertically beyond the first routing line in the first direction, the first routing line extends laterally beyond the first metal particle and the first metal pillar towards the first chip and extends vertically beyond the first chip and the first metal particle in the second direction, the first metal particle is devoid of solder and conductive adhesive, overlaps and is non-integral with the first routing line, the first conductive bond and the first metal pillar, is disposed outside the periphery of the first chip and extends vertically across at least some of a thickness of the first chip between the first and second surfaces of the first chip, the first conductive bond is solder or conductive adhesive, overlaps the first routing line and the first metal pillar and contacts and electrically connects the first routing line and the first metal particle, the first metal pillar is devoid of solder and conductive adhesive, contacts and is non-integral with the first routing line, is disposed outside the periphery of the first chip and extends vertically beyond the first chip, the first routing line, the first conductive bond, the first metal particle and the first encapsulant in the second direction, and any chip embedded in the first encapsulant is electrically connected to the first metal particle by an electrically conductive path that includes the first routing line;
• a second semiconductor chip assembly, comprising:
• a second semiconductor chip that includes first and second opposing surfaces, wherein the first surface of the second chip includes a second conductive pad;
• a second conductive trace that includes a second routing line, a second metal particle, a second conductive bond and a second metal pillar;
• a second connection joint that electrically connects the second routing line and the second pad;
• and
• a second encapsulant that includes first and second opposing surfaces, wherein the first surface of the second encapsulant faces in the first direction, the second surface of the second encapsulant faces in the second direction, a second aperture in the second encapsulant extends from the first surface of the second encapsulant to the second metal particle, extends into but not through the second encapsulant, is spaced from the second routing line and the second metal pillar and is disposed outside a periphery of the second chip, the second chip and the second metal particle are embedded in the second encapsulant, the second chip, the second metal particle and the second encapsulant extend vertically beyond the second routing line in the first direction, the second routing line extends laterally beyond the second metal particle and the second metal pillar towards the second chip and extends vertically beyond the second chip and the second metal particle in the second direction, the second metal particle is devoid of solder and conductive adhesive, overlaps and is non-integral with the second routing line, the second conductive bond and the second metal pillar, is disposed outside the periphery of the second chip and extends vertically across at least some of a thickness of the second chip between the first and second surfaces of the second chip, the second conductive bond is solder or conductive adhesive, overlaps the second routing line and the second metal pillar and contacts and electrically connects the second routing line and the second metal particle, the second metal pillar is devoid of solder and conductive adhesive, contacts and is non-integral with the second routing line, is disposed outside the periphery of the second chip and extends vertically beyond the second chip, the second routing line, the second conductive bond, the second metal particle and the second encapsulant in the second direction, and any chip embedded in the second encapsulant is electrically connected to the second metal particle by an electrically conductive path that includes the second routing line;
• and
• a conductive interconnect;
• wherein the first assembly overlaps the second assembly, the first surface of the second encapsulant faces towards the second surface of the first encapsulant, the first metal pillar extends into the second aperture, extends into and contacts and is embedded in and is electrically connected to the conductive interconnect within the second aperture and is disposed vertically beyond the second routing line in the first direction, the conductive interconnect contacts and electrically connects the first metal pillar and the second metal particle within the second encapsulant and is disposed vertically beyond the second routing line in the first direction, the first and second routing lines are spaced from and vertically aligned with one another, the first and second metal particles are spaced from and vertically aligned with one another, and the first and second metal pillars are spaced from and vertically aligned with one another.