Flip-chip type quad flat package and leadframe
AssigneeAdvanced Semiconductor Engineering, Inc.
InventorsHsueh-Te Wang, Meng-Jen Wang, Chi-Hao Chiu, Chien Liu
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AssigneeAdvanced Semiconductor Engineering, Inc.
InventorsHsueh-Te Wang, Meng-Jen Wang, Chi-Hao Chiu, Chien Liu
Estimating the term…
A flip-chip type quad flat package and a leadframe. The leadframe comprises a bump-connecting area and a non-connecting area. The maximum width of the bump-connecting area is larger than the width of the non-connecting area. A bump is limited to the bump-connecting area after performing a reflow process so that the bumps are prevented from collapsing, the manufacturing cost is reduced and the process is simplified.
A leadframe having a plurality of leads, wherein each lead comprises a bump-connecting area and a non-connecting area, the maximum width of each bump-connecting area is a first width while each non-connecting area has a second width, the first width is greater than the second width and the ratio of the first width to the second with is greater than 1.2.
A flip-chip type quad flat package, comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Chip-supporting parts, e.g. die pads: leadframe inner leads serving as die pads
Leadframes: shapes or dispositions
Additional interconnections in combination with leadframes: bumps or wires
Leadframes: specially adapted for cooling
Term ended 1 Nov 2024 (estimated)
This application claims the priority benefit of Taiwan application serial no. 92130406, filed on Oct. 31, 2003.
1. Field of the Invention
The present invention relates to a flip-chip type quad flat package (FC-QFP) and a leadframe. More particularly, the present invention relates to a flip-chip type quad flat package and a leadframe that can prevent abnormal collapse of bumps, lower the production cost and simplify the production process.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
FIG. 1 is a side view of a conventional quad flat non-leaded package.
FIG. 2 is a bottom view of the quad flat non-leaded package of FIG. 1.
Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
FIG. 5 is a side view of a flip-chip type quad flat package according one embodiment of the present invention. FIG. 6 is a bottom view of the flip-chip type quad flat package shown in FIG. 5. As shown in FIGS. 5 and 6, the quad flat non-leaded chip package 200 of the present invention mainly comprises a chip 210, a leadframe 220 and an encapsulant 230. The chip 210 has an active surface 212 and a corresponding back surface 214. The active surface 212 is a surface where the active devices are formed. The active surface 212 of the chip 210 further comprises a plurality of exposed bonding pads 216.
The leadframe 220 comprises a plurality of leads 222. Each lead 222 has a top surface 222a and a bottom surface 222b. In addition, the bonding pads 216 on the chip 210 are connected to the top surface 222aof the leads 222 through various bumps 240 so that the bonding pads 216 and the leads 222 are electrically connected. The encapsulant 230 encapsulates the chip 210, the bumps 240 and the top surface 222a of the leads 222 but exposes the bottom surface 222b of the leads 222 (as shown in FIG. 6). Furthermore, the leadframe 220 comprises a heat sink 224. The leads 222 are arranged adjacent to the edge of the heat sink 224, for example. The heat sink has a top surface 224a and a corresponding bottom surface 224b. Preferably, the bottom surface 224b of the heat sink 224 is exposed outside the encapsulant 230. The top surface 224a of the heat sink 224 may contact the back surface 214 of the chip 210 so that the heat sink 224 can dissipate the heat generated by the chip 210 away from the package and increase the heat-dissipating function.