Semiconductor device and a method of manufacturing the same
AssigneeRenesas Technology Corp.
InventorsHideki Aono, Kousuke Okuyama, Kozo Watanabe, Kenichi Kuroda
Life of this patent
Estimating the term…
Abstract
Semiconductor regions for the suppression of short channel effects are not provided for a pMIS and an nMIS that constitute an inverter circuit of an input first stage of an I/O buffer circuit, whereas semiconductor regions for the suppression of short channel effects are provided for pMIS and nMIS of inverter circuits of the next stage of an I/O buffer circuit.
Claims14
A semiconductor device comprising , a plurality of field effect transistors provided on a common semiconductor substrate and operated at different voltages, which plurality of field effect transistors includes field effect transistors which are higher in operating voltage than others of said plurality of field effect transistors;
- wherein in the field effect transistors which are higher in operating voltage, of the plurality of field effect transistors, a first field effect transistor, which directly receives a signal inputted from outside, is configured so as to differ in drain structure from a second field effect transistor thereof which indirectly receives the signal inputted from outside, and
- wherein the drain structure of the first field effect transistor differs from the drain structure of the second field effect transistor in that the drain structure of second field effect transistor includes regions of opposite conductivity to one another while the drain structure of the first field effect transistor does not include regions of opposite conductivity from one another.
A semiconductor device comprising a plurality of field effect transistors provided on a common semiconductor substrate and operated at different voltages, which plurality of field effect transistors includes field effect transistors which are higher in operating voltage than others of said plurality of field effect transistors;
- wherein in the field effect transistors which are higher in operating voltage, of the plurality of field effect transistors, a first field effect transistor, which directly receives a signal inputted from outside, is configured so as to differ in drain structure from a second field effect transistor thereof which indirectly receives the signal inputted from outside, and
- wherein the second field effect transistor indirectly receives the signal inputted from outside through the first field effect transistor.
Dependencies are inferred from the claim text.