US 7,067,881 B2Granted

Semiconductor device

AssigneeRenesas Technology Corp.

InventorsTakuji Matsumoto, Takashi Ipposhi, Toshiaki Iwamatsu, Yuuichi Hirano

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Abstract

A semiconductor device and its manufacturing method are provided which can properly avoid reduction of isolation breakdown voltage without involving adverse effects like an increase in junction capacitance. Impurity-introduced regions (11) are formed after a silicon layer (3) has been thinned through formation of recesses (14). Therefore n-type impurities are not implanted into the portions of the p-type silicon layer (3) that are located between the bottoms of element isolation insulating films (5) and the top surface of a BOX layer (2), which avoids reduction of isolation breakdown voltage. Furthermore, since the impurity-introduced regions (11) are formed to reach the upper surface of the BOX layer (2), the junction capacitance of source/drain regions (12) is not increased.

Claims6

Dependent claims

A semiconductor device comprising:

an SOI substrate having a semiconductor substrate, an insulating layer, and a semiconductor layer of a first conductivity type that are stacked in this order;
element isolation insulating films formed partially in a main surface of said semiconductor layer, with portions of said semiconductor layer interposed between said insulating layer and bottom surfaces of said element isolation insulating films;
a gate structure formed partially on said main surface of said semiconductor layer in an element formation region defined by said element isolation insulating films;
a pair of recesses formed in said element formation region, said recesses being formed in said main surface of said semiconductor layer in portions that are not covered by said gate structure, with a channel formation region under said gate structure interposed between said pair of recesses;
and
source/drain regions formed in bottom surfaces of said recesses and having a second conductivity type that is different from said first conductivity type, said source/drain regions forming a pair, with said channel formation region interposed therebetween, and having bottom surfaces or depletion layers that reach said insulating layer,
wherein the part of said main surface of said semiconductor layer on which said gate structure resides forms an angle larger than 90° with a corresponding side surface of each said recess.

4 more elements

A semiconductor device comprising:

an SOI substrate having a semiconductor substrate, an insulating layer, and a semiconductor layer of a first conductivity type that are stacked in this order;
element isolation insulating films formed partially in a main surface of said semiconductor layer, with portions of said semiconductor layer interposed between said insulating layer and bottom surfaces of said element isolation insulating films;
a gate structure formed partially on said main surface of said semiconductor layer in an element formation region defined by said element isolation insulating films;
a pair of recesses formed in said element formation region, said recesses being formed in said main surface of said semiconductor layer in portions that are not covered by said gate structure, with a channel formation region under said gate structure interposed between said pair of recesses;
and
source/drain regions formed in bottom surfaces of said recesses and having a second conductivity type that is different from said first conductivity type, said source/drain regions forming a pair, with said channel formation region interposed therebetween, and having bottom surfaces or depletion layers that reach said insulating layer,
wherein said source/drain regions comprise:
first impurity-introduced regions having a relatively low concentration and formed in said main surface of said semiconductor layer;
and
second impurity-introduced regions having a relatively high concentration and formed deeper than said first impurity-introduced regions,
wherein a depth from said main surface of said semiconductor layer to said bottom surface of each said recess is smaller than a depth from said main surface of said semiconductor layer to a bottom surface of each said first impurity-introduced region.

8 more elements

A semiconductor device comprising:

an SOI substrate having a semiconductor substrate, an insulating layer, and a semiconductor layer of a first conductivity type that are stacked in this order;
element isolation insulating films formed partially in a main surface of said semiconductor layer, with portions of said semiconductor layer interposed between said insulating layer and bottom surfaces of said element isolation insulating films;
a gate structure formed partially on said main surface of said semiconductor layer in an element formation region defined by said element isolation insulating films;
a pair of recesses formed in said element formation region, said recesses being formed in said main surface of said semiconductor layer in portions that are not covered by said gate structure, with a channel formation region under said gate structure interposed between said pair of recesses;
and
source/drain regions formed in bottom surfaces of said recesses and having a second conductivity type that is different from said first conductivity type, said source/drain regions forming a pair, with said channel formation region interposed therebetween, and having bottom surfaces or depletion layers that reach said insulating layer,
wherein said source/drain regions comprise:
first impurity-introduced regions having a relatively low concentration and formed in said main surface of said semiconductor layer;
second impurity-introduced regions having a relatively high concentration and formed deeper than said first impurity-introduced regions;
and
third impurity-introduced regions formed in said main surface of said semiconductor layer,
wherein a depth from said main surface of said semiconductor layer to bottom surfaces of said third impurity-introduced regions is greater than a depth from said main surface of said semiconductor layer to bottom surfaces of said first impurity-introduced regions, and
wherein a depth from said main surface of said semiconductor layer to said bottom surfaces of said recesses is smaller than a depth from said main surface of said semiconductor layer to said bottom surfaces of said third impurity-introduced regions.

10 more elements

A semiconductor device comprising:

an SOI substrate having a semiconductor substrate, an insulating layer, and a semiconductor layer of a first conductivity type that are stacked in this order;
element isolation insulating films formed partially in a main surface of said semiconductor layer, with portions of said semiconductor layer interposed between said insulating layer and bottom surfaces of said element isolation insulating films;
a gate structure formed partially on said main surface of said semiconductor layer in an element formation region defined by said element isolation insulating films;
a pair of recesses formed in said element formation region, said recesses being formed in said main surface of said semiconductor layer in portions that are not covered by said gate structure, with a channel formation region under said gate structure interposed between said pair of recesses;
and
source/drain regions formed in bottom surfaces of said recesses and having a second conductivity type that is different from said first conductivity type, said source/drain regions forming a pair, with said channel formation region interposed therebetween, and having bottom surfaces or depletion layers that reach said insulating layer,
wherein said gate structure comprises:
a gate insulating film formed on said main surface of said semiconductor layer;
a gate electrode formed on said gate insulating film;
and
first sidewalls formed on sides of said gate electrode;
and wherein said semiconductor device further comprises:
second sidewalls formed on said bottom surfaces of said recesses and in contact with said first sidewalls;
and
metal-semiconductor compound layers formed on said source/drain regions in portions that are not covered by said second sidewalls.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/754,539Filed 12 Jan 2004
Priority: JP 2003-00664115 Jan 2003
Published: US 2004/0227185 A118 Nov 2004
Granted: 27 Jun 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

H10D 64/017
Manufacture or treatment: using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e.…
H10D 30/0212
Of FETs having insulated gates [IGFET]: using self-aligned silicidation
H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…
H10D 30/608
Having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs: having non-planar bodies, e.g. having recessed gate electrodes