Integration of trench power transistors into a 1.5 μm BCD process

A BCD device including connected CMOS and vertical trench DMOS devices, comprising:

• a plurality of layers formed on a semiconductor substrate, the plurality of layers including an epitaxial layer having a first surface;
• a CMOS device formed in at least one of the plurality of layers;
• and
• a trench DMOS device formed in the epitaxial layer and connected to the CMOS device, the trench DMOS device including:
• a trench region in the epitaxial layer extending from the first surface, the trench region including an active portion and a gate contact portion, the active portion containing a doped polysilicon operable to act as a gate for the trench DMOS device;
• a heavily doped source region in the epitaxial layer extending from the first surface and adjacent the active portion of the trench region, the heavily doped source region operable to act as a source for the trench DMOS device;
• and
• a doped channel region formed adjacent the heavily-doped source region, opposite the first surface, and the doped polysilicon region, whereby the doped channel region is operable to act as a channel of the trench DMOS device and the epitaxial layer is operable to act as a drain for the trench DMOS device, whereby current flows from the source to the drain through the channel in a direction substantially away from the first surface.