Stacked gate semiconductor memory
AssigneeKabushiki Kaisha Toshiba
InventorYoshio Ozawa
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Abstract
A semiconductor memory embraces a plurality of memory cell transistors, and each of the memory cell transistors encompasses a substrate; a gate insulator stacked on the substrate, configured to enable tunneling of electrons through the gate insulator; a floating gate electrode stacked on the gate insulator, configured to accumulate electron charges; an inter-electrode dielectric stacked on the floating gate electrode incorporating a positive charge layer, distribution of the positive charge layer being localized in the lower half of the inter-electrode dielectric; and a control gate electrode stacked on the inter-electrode dielectric.
Claims4
A semiconductor memory comprising a plurality of memory cell transistors, each of the memory cell transistors comprising:
- a substrate;
- a gate insulator stacked on the substrate, configured to enable tunneling of electrons through the gate insulator;
- a floating gate electrode stacked on the gate insulator, configured to accumulate electron charges;
- an inter-electrode dielectric stacked on the floating gate electrode incorporating a positive charge layer, distribution of the positive charge layer being localized in the lower half of the inter-electrode dielectric;
- and
- a control gate electrode stacked on the inter-electrode dielectric.
Dependencies are inferred from the claim text.