Method for etch-stop layer etching during damascene dielectric etching with low polymerization

A method for manufacturing an integrated circuit, comprising:

• forming transistors over a semiconductor substrate;
• forming a first dielectric layer over the transistor;
• depositing a hardmask on the dielectric layer;
• placing an anti-reflective layer on the hardmask;
• conducting a first etch through a second dielectric layer located over an etch-stop layer, the second dielectric layer having a photoresist layer located thereover and the first etch being selective to the etch-stop;
• conducting a second etch different from the first etch on the etch-stop, the second etch comprising a mixture of gases wherein an etching gas comprises tetrafluoromethane and an etch rate modulator includes a mixture of argon, oxygen and nitrogen and wherein the ratio of a flow rate of tetrafluoromethane to a flaw rate of the oxygen is about 3:1, the ratio of the flow rate of tetrafluoromethane to a flow rate of argon is about 3:70, the ratio of the flow rate of tetrafluoromethane to a flow rate of nitrogen is about 3:20, and the weighted average ratio of nitrogen to carbon is greater than about 10:1;
• forming additional dielectric layers over the first dielectric layer;
• and
• forming interconnects with the first dielectric layer and the additional dielectric layers to interconnect the transistors and thereby form an operative integrated circuit.