Method of fabricating high yield wafer level packages integrating MMIC and MEMS components

#This invention relates generally to integrated circuit fabrication techniques and, more particularly, to methods for integrating monolithic microwave integrated circuit (MMIC) and micro electromechanical systems (MEMS) components into a single package. MMIC technology necessitates the use of an extremely thin substrate, in the range of 50–100 μm, and a MEMS device necessarily has significant thickness because it is basically a three-dimensional device. Moreover, MEMS devices cannot operate reliably in the field without hermetic packaging.

#Integration of MEMS devices, such as radio frequency (RF) MEMS switches, with MMIC technology offers significant system performance improvements, such as low loss, high linearity and added functionality, in many space and military applications, especially those operating at very high frequencies, e.g., approaching 500 GHz (gigahertz) and above. There are, however, practical difficulties inherent in combining the two technologies. MMIC components are formed in one face of a very thin substrate and employ conductive vias to make connections through the “back” face of the substrate, while MEMS devices are preferably formed in a three-dimensional, hermetically sealed cavity, which dictates the use of a mechanically sturdy package. Reconciling the needs of MMIC components with those of MEMS components in an integrated package is one important goal of the present invention. A related goal is to achieve cost savings of the type normally associated with wafer-level fabrication and packaging of integrated circuitry, but in this case rendered very difficult to achieve by the thin substrate structure of MMIC components.

#The present invention resides in a technique for integrating MMIC (monolithic microwave integrated circuit) technology with MEMS (micro electromechanical systems) technology in a double-wafer structure. Briefly, and in general terms, the method of the invention comprises the steps of providing a substrate wafer having a front face and a back face, and providing a cover wafer of comparable size to the substrate wafer; fabricating multiple MMIC and MEMS components on the front face of the substrate wafer; forming a first set of seal rings around selected device areas on the front face of the substrate wafer; forming a second set of seal rings on a surface of the cover wafer, in positions corresponding the first set of seal rings; and then bonding the first and second sets of seal rings to provide a double-wafer structure that includes multiple device cavities formed between the substrate wafer and the cover wafer. The ensuing steps include thinning the substrate wafer by removing material from its back face; and completing the MMIC and MEMS fabrication on the back face of the thinned substrate wafer. Integration of MMIC and MEMS components provides enhanced circuit performance for each fabricated device.

#FIGS. 1A–1F are cross-sectional views that together depict a process for fabrication of wafer-level packages that integrate MEMS and MMIC components in multiple device cavities, only one of which is shown.

#FIG. 2 is a diagrammatic top view of a MEMS/MMIC wafer such as the one shown in FIG. 1A.

#FIG. 3 is a diagrammatic cross-sectional view similar FIG. 1E, illustrating (with FIG. 2) a guard ring concept utilized in the fabrication process.

#As shown in the drawings for purposes of illustration, the present invention concerns a process for wafer-level fabrication of circuitry that integrates MMIC (monolithic microwave integrated circuit) technology and MEMS (micro electromechanical systems) components. Although significant performance benefits can be achieved by this integration of technologies, differences in their fabrication and packing requirements have made this goal an elusive one for designers. One difficulty in particular is that production yields are rendered extremely low because of the required thinness of a MMIC substrate and a resultant tendency of the substrate to crack or break during wafer-level fabrications steps.

#In accordance with the present invention, MMIC and MEMS components are integrated into a double-wafer structure that overcomes the foregoing difficulties. The principles of the fabrication process are shown in diagrammatic form in FIGS. 1A–1F. In particular, FIG. 1A shows the cross section of a portion of a MEMS/MMIC wafer, indicated by reference numeral 10. The first step of the process is to fabricate on the “front” side of the wafer 10 one or more MMIC components, depicted by the rectangle 12, and one or more MEMS components, illustrated by the irregular outline 14. The MEMS component 14, which may be a radio-frequency (RF) switch, in general includes a portion recessed into the substrate 10 and a portion extending above the substrate. Moreover, the MEMS component 14 is preferably enclosed in a hermetically sealed cavity. To this end, the structure of FIG. 1A further includes a seal ring, one component of which is shown at 16. FIG. 1B shows the cross-section of a cover substrate 20, which also includes a seal ring component 22. When the seal ring components 16 and 22 are bonded together, using a process to be described below in more detail, a double-wafer structure results, as shown in FIG. 1C, and a cavity 24 is formed between the substrates 10 and 20.

#A critical ensuing step is thinning the wafer 10 of FIG. 1C, after first mounting the double-wafer structure to a dummy carrier 26 by the cover wafer 20, to produce the significantly thinned wafer 10′ depicted in FIG. 1D. A combination of lapping, polishing and etching steps may be employed to thin the wafer 10. For example, the wafer 10 may be approximately 750 μm thick in FIG. 1C at the start of the thinning step. An initial lapping step may be initially used to reduce the thickness to approximately 160 μm. Lapping is essentially a process of removing material from a surface by use of a lapping tool (or by hand) and an abrasive material, usually suspended in a liquid. After lapping, a mechanical polishing step may be used, further reducing the thickness to approximately 150 μm. Finally, a chemical etching step reduces the wafer thickness further to approximately 100 μm or less, depending on the requirements of MMIC fabrication. The thinning step may alternatively include grinding material from the wafer 10. More generally, the thinning step includes any combination of process steps that remove material from and maintain the flatness of the “back” face of the substrate wafer.