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US 7,067,394 B2Granted
Manufacturing of monolithically integrated pin structures
AssigneeIntel Corporation
InventorDaniel So
Life of this patent
Estimating the term…
Abstract
Fabrication techniques for fabricating p-i-n structures that achieve a thin intrinsic layer and a small resistance across the p-i-n structure and thus a high response speed in a monolithically integrated circuit package. Germanium p-i-n structures may be fabricated over silicon or silicon-on-insulator substrates using silicon processing technologies.
Claims31
A method, comprising:
- applying an ion implantation process to implant dopant ions of a first conductivity type to one side of a donor wafer;
- performing a rapid thermal annealing process to anneal the doped one side to form a first conductive layer;
- bonding a handle wafer to the first conductive layer;
- thinning at least a portion of the donor wafer to leave one layer of the donor wafer above the first conductive layer;
- applying another ion implantation process to implant dopant ions of a second conductivity type to the one layer to form a second conductive layer while maintaining an intrinsic layer between the first and the second conductive layers;
- and
- performing another rapid thermal annealing process to anneal the second conductive layer.
4 more elements
A method, comprising:
- applying an ion implantation process to implant dopant ions of a first conductivity type to one side of a donor wafer at a concentration of about 1019 cm−3 or higher;
- performing a rapid thermal annealing process for a duration of tens of seconds or less to anneal the doped one side to form a first conductive layer;
- bonding a handle wafer to the first conductive layer;
- thinning at least a portion of the donor wafer to leave one layer of the donor wafer above the first conductive layer;
- applying another ion implantation process to implant dopant ions of a second conductivity type to the one layer at a concentration of about 1019 cm−3 or higher to form a second conductive layer while maintaining an intrinsic layer between the first and the second conductive layers;
- and
- performing another rapid thermal annealing process for a duration of tens of seconds or less to anneal the second conductive layer.
4 more elements
A method, comprising:
- applying an ion implantation process to implant dopant ions of a first conductivity type to one side of a donor wafer comprising germanium at a concentration of about 1019 cm−3 or higher;
- performing a rapid thermal annealing process for a duration of tens of seconds or less to anneal the doped one side to form a first conductive layer;
- bonding a handle wafer suitable for silicon processing to the first conductive layer;
- thinning at least a portion of the donor wafer to leave one layer of the donor wafer above the first conductive layer;
- applying another ion implantation process to implant dopant ions of a second conductivity type to the one layer at a concentration of about 1019 cm−3 or higher to form a second conductive layer while maintaining an intrinsic layer between the first and the second conductive layers;
- and
- performing another rapid thermal annealing process for a duration of tens of seconds or less to anneal the second conductive layer.
4 more elements
Dependencies are inferred from the claim text.