Method to form a metal silicide gate device

A method to form metal silicide gates in the fabrication of an integrated circuit device, said method comprising:

• forming polysilicon lines overlying a substrate wherein said polysilicon lines have dielectric sidewalls;
• forming a first isolation layer overlying said substrate and said dielectric sidewalls wherein said first isolation layer does not overlie the top surface of said polysilicon lines;
• partially etching down said polysilicon lines such that said top surfaces of said polysilicon lines are below the top surface of said dielectric sidewalls;
• thereafter depositing a metal layer overlying said polysilicon lines;
• thermally annealing to completely convert said polysilicon lines to metal suicide gates;
• and
• removing unreacted said metal layer to complete said device;
• wherein a dielectric layer between said substrate and a first group of said metal suicide gates has a first thickness, wherein a dielectric layer between said substrate and a second group of said metal silicide gates has a second thickness, and wherein said first and second thicknesses are not equal.

A method to form metal suicide gates in the fabrication of an integrated circuit device, said method comprising:

• forming a dielectric layer overlying a substrate;
• depositing a polysilicon layer overlying said dielectric layer;
• depositing a hard mask layer overlying said polysilicon layer;
• patterning said hard mask layer;
• patterning said polysilicon layer to form polysilicon lines as defined by said hard mask layer pattern;
• forming a first isolation layer overlying said substrate and said polysilicon lines wherein said first isolation layer does not overlie said hard mask layer;
• removing said hard mask layer;
• thereafter partially etching down said polysilicon lines such that the top surfaces of said polysilicon lines are below the top surface of said first isolation layer;
• thereafter depositing a metal layer overlying said polysilicon lines;
• thermally annealing to completely convert said polysilicon lines to metal silicide gates;
• and
• removing unreacted said metal layer to complete said device;
• implanting ions into said substrate prior to said step of forming a first isolation layer to thereby form first doped regions in said substrate and adjacent to said polysilicon lines, wherein said step of forming a first isolation layer further comprises:
• depositing a spacer layer overlying said substrate and said substrate and said polysilicon lines, etching back said spacer layer to form spacers on said sidewalls of said polysilicon lines, and implanting ions into said substrate to thereby form second doped regions in said substrate and adjacent to said spacers;
• depositing a second metal layer overlying said substrate, said spacers, and said hard mask layer;
• thermally annealing to convert a part of said substrate in said second doped regions to metal suicide;
• and
• removing unreacted said second metal layer.

A method to form metal silicide gates in the fabrication of an integrated circuit device, said method comprising:

• forming a dielectric layer overlying a substrate;
• depositing a polysilicon layer overlying said dielectric layer;
• depositing a hard mask layer overlying said polysilicon layer;
• patterning said hard mask layer;
• patterning said polysilicon layer to form polysilicon lines as defined by said hard mask layer pattern;
• forming a first isolation layer overlying said substrate and said polysilicon lines wherein said first isolation layer does not overlie said hard mask layer;
• removing said hard mask layer;
• thereafter partially etching down said polysilicon lines such that the top surfaces of said polysilicon lines are below the top surface of said first isolation layer;
• thereafter depositing a metal layer overlying said polysilicon lines;
• thermally annealing to completely convert said polysilicon lines to metal suicide gates;
• and
• removing unreacted said metal layer to complete said device.
• wherein said dielectric layer for a first group of said metal silicide gates is a first thickness, wherein said dielectric layer for a second group of said metal silicide gates is a second thickness, and wherein said first and second thicknesses are not equal.